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1. 发明授权

US08854077B2 Low leakage and data retention circuitry 有权
标题翻译：低泄漏和数据保持电路
公开(公告)号：US08854077B2
公开(公告)日：2014-10-07
申请号：US13569613
申请日：2012-08-08
申请人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： H03K19/17
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
摘要翻译：集成电路包括第一电路和睡眠晶体管电路。第一个电路接收输入信号并处理输入信号。第一电路还保持具有低泄漏的睡眠状态的数据。睡眠晶体管电路耦合到第一电路并且接收具有负电压的睡眠信号。休眠电路降低处于休眠状态的第一电路的功耗，以便在将数据保留在第一电路中的同时基于睡眠信号具有低泄漏。

2. 发明申请

US20110260785A1 Low Leakage and Data Retention Circuitry 有权
标题翻译：低泄漏和数据保留电路
公开(公告)号：US20110260785A1
公开(公告)日：2011-10-27
申请号：US13074291
申请日：2011-03-29
申请人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： G05F1/10
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
摘要翻译：集成电路包括第一电路和睡眠晶体管电路。第一个电路接收输入信号并处理输入信号。第一电路还保持具有低泄漏的睡眠状态的数据。睡眠晶体管电路耦合到第一电路并且接收具有负电压的睡眠信号。休眠电路降低处于休眠状态的第一电路的功耗，以便在将数据保留在第一电路中的同时基于睡眠信号具有低泄漏。

3. 发明授权

US07443197B2 Low leakage and data retention circuitry 有权
公开(公告)号：US07443197B2
公开(公告)日：2008-10-28
申请号：US11998725
申请日：2007-11-30
申请人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： H03K19/173
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

4. 发明授权

US4947060A High speed complimentary output stage utilizing current steering transistors and a single current source 失效
标题翻译：高速互补输出级采用电流转向晶体管和单个电流源
公开(公告)号：US4947060A
公开(公告)日：1990-08-07
申请号：US325402
申请日：1989-03-17
申请人： Barry A. Hoberman , William E. Moss
发明人： Barry A. Hoberman , William E. Moss
IPC分类号： H03K19/173 , G06F7/00 , H03K19/00 , H03K19/018 , H03K19/177
CPC分类号： H03K19/0016 , H03K19/01806 , H03K19/17708
摘要： A novel output stage is disclosed which includes first and second output transistors for providing complementary output signals at inverting and noninverting output terminals in response to receipt of an input signal, wherein the output stage includes a single source of current and a pair of current steering transistors which are controlled by circuit means coupled between the input terminal and the control terminals of the current steering transistors to turn on the one of the current steering transistors which is coupled to the one of the inverting and noninverting output terminals which is undergoing a high voltage to low voltage transition and to turn off the other of the current steering transistors in response to the change of state of the input signal received at an input terminal.
摘要翻译：公开了一种新颖的输出级，其包括第一和第二输出晶体管，用于响应于输入信号的接收而在反相和同相输出端提供互补输出信号，其中输出级包括单个电流源和一对电流转向晶体管其由耦合在当前转向晶体管的输入端子和控制端子之间的电路装置控制，以接通耦合到正在经历高电压的反相和同相输出端子之一的电流转向晶体管中的一个，低电压转换，并且响应于在输入端子处接收的输入信号的状态的改变而关闭另一个电流转向晶体管。

5. 发明授权

US4864165A ECL programmable logic array with direct testing means for verification of programmed state 失效
标题翻译： ECL可编程逻辑阵列，具有用于验证编程状态的直接测试手段
公开(公告)号：US4864165A
公开(公告)日：1989-09-05
申请号：US141239
申请日：1988-01-05
申请人： Barry A. Hoberman , William E. Moss
发明人： Barry A. Hoberman , William E. Moss
IPC分类号： H03K19/173 , G06F7/00 , H03K19/00 , H03K19/018 , H03K19/177
CPC分类号： H03K19/0016 , H03K19/01806 , H03K19/17708
摘要： A novel ECL Programmable Logic Array (PLA) is provided which operates as an ECL PLA, having ECL voltage level compatible input and output leads, thereby providing a high-speed PLA. A unique programming means is provided which allows the ECL PLA to be programmed using TTL-compatible programming voltage levels, such as are provided by common and inexpensive prior art TTL PLA programmers. In another embodiment higher speed is achieved by the design of each sense amplifier using emitter function logic such that the sense transistor and load functions a cascode amplifier. In another embodiment a lower power PLA device is achieved by utilizing a switched current source pull down means for pulling down the rows of the PLA array. In another embodiment low power and user convenience is achieved by allowing each pair of output terminals to share a predefined set of product terms. In another embodiment of this invention, each output terminal is capable of having its output polarity programmed, in order to provide either a desired product term, or the inverse of that product term.
摘要翻译：提供了一种新型的ECL可编程逻辑阵列（PLA），其作为ECL PLA工作，具有ECL电压电平兼容的输入和输出引线，从而提供高速PLA。提供了一种独特的编程手段，使得ECL PLA可以使用TTL兼容的编程电压电平进行编程，例如由普通和便宜的现有技术TTL PLA编程器提供。在另一个实施例中，通过使用发射器功能逻辑的每个读出放大器的设计实现更高的速度，使得感测晶体管和负载对共源共栅放大器起作用。在另一个实施例中，通过利用用于下拉PLA阵列的行的开关电流源下拉装置来实现较低功率的PLA装置。在另一个实施例中，通过允许每对输出终端共享预定义的一组产品项来实现低功率和用户便利性。在本发明的另一个实施例中，每个输出端子能够对其输出极性进行编程，以便提供期望的乘积项或该乘积项的倒数。

6. 发明授权

US07940081B2 Low leakage and data retention circuitry 有权
标题翻译：低泄漏和数据保持电路
公开(公告)号：US07940081B2
公开(公告)日：2011-05-10
申请号：US12542352
申请日：2009-08-17
申请人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： H03K19/173
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
摘要翻译：集成电路包括第一电路和睡眠晶体管电路。第一个电路接收输入信号并处理输入信号。第一电路还保持具有低泄漏的睡眠状态的数据。睡眠晶体管电路耦合到第一电路并且接收具有负电压的睡眠信号。休眠电路降低处于休眠状态的第一电路的功耗，以便在将数据保留在第一电路中的同时基于睡眠信号具有低泄漏。

7. 发明授权

US4814646A Programmable logic array using emitter-coupled logic 失效
标题翻译：使用发射极耦合逻辑的可编程逻辑阵列
公开(公告)号：US4814646A
公开(公告)日：1989-03-21
申请号：US715141
申请日：1985-03-22
申请人： Barry A. Hoberman , William E. Moss
发明人： Barry A. Hoberman , William E. Moss
IPC分类号： H03K19/173 , G06F7/00 , H03K19/00 , H03K19/018 , H03K19/177 , H03K19/086
CPC分类号： H03K19/0016 , H03K19/01806 , H03K19/17708
摘要： An ECL Programmable Logic Array (PLA) having ECL voltage level compatible input and output leads, thereby providing a high-speed PLA. A unique programming means is provided which allows the ECL PLA to be programmed using TTL-compatible programming voltage levels, such as are provided by common and inexpensive prior art TTL PLA programmers. In another embodiment higher speed is achieved by the design of each sense amplifier using emitter function logic such that the sense transistor and load functions a cascode amplifier. In another embodiment a lower power PLA device is achieved by utilizing a switched current source pull down means for pulling down the rows of the PLA array. In another embodiment low power and user convenience is achieved by allowing each pair of output terminals to share a predefined set of product terms. In another embodiment of this invention, each output terminal is capable of having its output polarity programmed, in order to provide either a desired product term, or the inverse of that product term.

8. 发明授权

US4574367A Memory cell and array 失效
标题翻译：存储单元和数组
公开(公告)号：US4574367A
公开(公告)日：1986-03-04
申请号：US551736
申请日：1983-11-10
申请人： Barry A. Hoberman , William E. Moss
发明人： Barry A. Hoberman , William E. Moss
IPC分类号： G11C11/414 , G06F5/08 , G11C11/411 , G11C11/40
CPC分类号： G06F5/08
摘要： A fall-through memory array comprising in a plurality of rows and columns a plurality of memory cells, each memory cell comprising a pair of cross-coupled transistors having three emitters, a collector and a base. Control potentials applied to a word line, coupled to each one of two of the emitters of each of the transistors, control the transfer of data bits from one row of such memory cells to another.
摘要翻译：一种包括多个行和列的多个存储单元的跌落式存储器阵列，每个存储单元包括一对具有三个发射极的交叉耦合晶体管，一个集电极和一个基极。耦合到每个晶体管的两个发射极中的每一个的字线上的控制电位控制数据位从这种存储单元的一行到另一行的传输。

9. 发明申请

US20100060319A1 LOW LEAKAGE AND DATA RETENTION CIRCUITRY 有权
标题翻译：低泄漏和数据保持电路
公开(公告)号：US20100060319A1
公开(公告)日：2010-03-11
申请号：US12542352
申请日：2009-08-17
申请人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： H03K19/094
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
摘要翻译：集成电路包括第一电路和睡眠晶体管电路。第一个电路接收输入信号并处理输入信号。第一电路还保持具有低泄漏的睡眠状态的数据。睡眠晶体管电路耦合到第一电路并且接收具有负电压的睡眠信号。休眠电路降低处于休眠状态的第一电路的功耗，以便在将数据保留在第一电路中的同时基于睡眠信号具有低泄漏。

10. 发明授权

US07592837B2 Low leakage and data retention circuitry 有权
标题翻译：低泄漏和数据保持电路
公开(公告)号：US07592837B2
公开(公告)日：2009-09-22
申请号：US12284311
申请日：2008-09-19
申请人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： H03K19/0175
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
摘要翻译：集成电路包括第一电路和睡眠晶体管电路。第一个电路接收输入信号并处理输入信号。第一电路还保持具有低泄漏的睡眠状态的数据。睡眠晶体管电路耦合到第一电路并且接收具有负电压的睡眠信号。休眠电路降低处于休眠状态的第一电路的功耗，以便在将数据保留在第一电路中的同时基于睡眠信号具有低泄漏。

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