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11. 发明授权

US06687154B2 Highly-integrated flash memory and mask ROM array architecture 有权
标题翻译：高度集成的闪存和掩模ROM阵列架构
公开(公告)号：US06687154B2
公开(公告)日：2004-02-03
申请号：US10364033
申请日：2003-02-11
申请人： Peter W. Lee , Fu-Chang Hsu
发明人： Peter W. Lee , Fu-Chang Hsu
IPC分类号： G11C1604
CPC分类号： H01L27/1126 , G11C11/005 , G11C16/0433 , G11C17/12 , H01L27/112 , H01L27/115
摘要： A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.
摘要翻译：实现了存储单元装置。存储单元器件包括具有栅极，漏极和源极的第一晶体管。第二个晶体管具有栅极，漏极和源极。第一晶体管漏极耦合到阵列位线。第二晶体管源耦合到阵列源极线。第一晶体管源耦合到第二晶体管漏极。第一晶体管和第二晶体管包括一个闪存晶体管和一个掩模ROM晶体管。可以读取掩模ROM晶体管的编程状态。

12. 发明授权

US06660585B1 Stacked gate flash memory cell with reduced disturb conditions 有权
标题翻译：具有减少干扰条件的堆叠式门闪存单元
公开(公告)号：US06660585B1
公开(公告)日：2003-12-09
申请号：US09531787
申请日：2000-03-21
申请人： Peter W. Lee , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen , Fu-Chang Hsu
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , G11C16/0416 , H01L21/28273
摘要： In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.
摘要翻译：在本发明中，公开了一种堆叠栅极闪存单元，其在器件的漏极侧具有轻掺杂漏极（LDD），并且使用源使用热电子发生进行编程并使用Fowler-Nordheim隧道擦除浮动栅极。通过利用LDD和使用源进行编程和擦除的单元的偏置来减少干扰条件。作为减少热电子产生的LDD的结果，漏极的电场大大减小。 LDD还有助于在编程期间减少位线干扰条件。通过将未选择的单元的位线预处理为Vcc，使未选择的单元中的瞬态位线干扰条件最小化。

13. 发明授权

US06584034B1 Flash memory array structure suitable for multiple simultaneous operations 有权
标题翻译：闪存阵列结构适用于多个同时操作
公开(公告)号：US06584034B1
公开(公告)日：2003-06-24
申请号：US10131271
申请日：2002-04-23
申请人： Fu-Chang Hsu , Peter W. Lee , Hsing-Ya Tsao
发明人： Fu-Chang Hsu , Peter W. Lee , Hsing-Ya Tsao
IPC分类号： G11C800
CPC分类号： G11C16/10 , G11C7/18 , G11C8/12 , G11C2216/22
摘要： In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.
摘要翻译：在本发明中公开了一种用于同时读和写操作的闪速存储器。存储器被划分成多个扇区，每个扇区具有扇区解码器。扇区解码器将多个主位线连接到每个存储器扇区内所包含的多个子位线。虽然可以使用包括2M解码器和分层式解码器的其他解码器，但是使用解码器来解释本发明。存储器阵列可以由各种架构进行配置，包括NOR，OR，NAND，AND，Dual-String和DINOR。存储器单元可以由包括ETOX，FLOTOX，EPROM，EEPROM，分离栅极和PMOS的各种阵列结构形成。

14. 发明授权

US06374770B1 Apparatus for improving film stability of halogen-doped silicon oxide films 失效
标题翻译：用于提高卤素掺杂氧化硅膜的膜稳定性的装置
公开(公告)号：US06374770B1
公开(公告)日：2002-04-23
申请号：US09597856
申请日：2000-06-20
申请人： Peter W. Lee , Stuardo Robles , Anand Gupta , Virendra V. S. Rana , Amrita Verma
发明人： Peter W. Lee , Stuardo Robles , Anand Gupta , Virendra V. S. Rana , Amrita Verma
IPC分类号： C23C1600
CPC分类号： H01L21/02131 , C23C16/401 , C23C16/56 , H01L21/02274 , H01L21/0234 , H01L21/02362 , H01L21/3105 , H01L21/31629
摘要： A chemical vapor deposition system that includes a housing configured to form a processing chamber, a substrate holder configured to hold a substrate within the processing chamber, a gas distribution system configured to introduce gases into the processing chamber, a plasma generation system configured to form a plasma within the processing chamber, a processor operatively coupled to control the gas distribution system and the plasma generation system, and a computer-readable memory coupled to the processor that stores a computer-readable program which directs the operation of the chemical vapor deposition system. In one embodiment the computer-readable program comprises instructions that control the gas distribution system to flow a process gas comprising silicon, oxygen and a halogen family member into the chamber to deposit a halogen-doped silicon oxide film on a substrate positioned on the substrate holder and instructions that control the gas distribution system and plasma generation system to densify the halogen-doped silicon oxide film by bombarding the film with ionic species from a plasma of an argon-containing gas source. In another embodiment, the computer-readable program comprises instructions that control the gas distribution system to flow a process gas comprising silicon, oxygen and a halogen family member into the chamber to deposit a halogen-doped silicon oxide film on said substrate and instructions that control the gas distribution system and plasma generation system to form a plasma from a hydrogen containing source gas to bombard the halogen-doped silicon oxide film with hydrogen ions to remove loosely bound halogen atoms from the film.
摘要翻译：一种化学气相沉积系统，其包括构造成形成处理室的壳体，被配置为在处理室内保持衬底的衬底保持器，配置成将气体引入到处理室中的气体分配系统;等离子体生成系统，处理室内的等离子体，可操作地耦合以控制气体分配系统和等离子体生成系统的处理器以及耦合到处理器的计算机可读存储器，其存储引导化学气相沉积系统的操作的计算机可读程序。在一个实施例中，计算机可读程序包括控制气体分配系统以将包含硅，氧和卤素族成员的工艺气体流入室中的指令，以将沉积卤素掺杂的氧化硅膜沉积在位于衬底保持器以及控制气体分配系统和等离子体发生系统通过用来自含氩气体源的等离子体的离子物质轰击膜来致密化掺杂氧化硅膜的指令。在另一个实施例中，计算机可读程序包括控制气体分配系统以使包含硅，氧和卤素族成员的工艺气体流入腔室中以在所述衬底上沉积卤素掺杂的氧化硅膜的指令，以及控制气体分配系统和等离子体发生系统，以形成来自含氢源气体的等离子体，用氢离子轰击卤素掺杂的氧化硅膜，以从薄膜中去除松散结合的卤素原子。

15. 发明授权

US5796657A Flash memory with flexible erasing size from multi-byte to multi-block 失效
标题翻译： Flash存储器具有从多字节到多块的灵活擦除大小
公开(公告)号：US5796657A
公开(公告)日：1998-08-18
申请号：US691281
申请日：1996-08-01
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C8/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/00
CPC分类号： G11C8/08 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3413 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C8/10 , H01L27/115 , G11C16/24 , G11C2211/5642 , G11C2211/5644 , G11C2216/20 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： A flash memory with a flexible erasing size includes a first bank of flash transistors and a second bank of flash transistors. Each bank of flash transistors forms a plurality of rows and a plurality of columns, each transistor having a gate, drain and source, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the first bank are all coupled to a first sourceline and the sources of the transistors in the second bank are all coupled to a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline, where the wordline decoder includes a wordline latch configured to latch the selected wordline. A sourceline decoder is coupled to the sourcelines and configured to receive a sourceline address signal and to decode the sourceline address signal to select a sourceline, where the sourceline decoder includes a sourceline latch configured to latch the selected sourceline. A bitline decoder is coupled to the bitlines and configured to receive a bitline address signal and to decode the bitline address signal to latch a selected bitline, where the bitline decoder includes a bitline latch configured to latch the selected bitline.
摘要翻译：具有柔性擦除尺寸的闪速存储器包括闪存晶体管的第一组和闪存晶体管的第二组。每个闪存晶体管组形成多个行和多个列，每个晶体管具有栅极，漏极和源极，其中每行中的晶体管的栅极耦合到公共字线，每列中的晶体管的漏极耦合到公共位线和第一组中的晶体管的源极都耦合到第一源极线，并且第二组中的晶体管的源极都耦合到第二源极线。字线解码器被耦合到字线并被配置为接收字线地址信号并且解码字线地址信号以选择字线，其中字线解码器包括配置成锁存所选字线的字线锁存器。源线解码器被耦合到源极线并且被配置为接收源线地址信号并且解码源线地址信号以选择源极线，其中源极线解码器包括被配置为锁存所选择的源极线的源极线锁存器。位线解码器耦合到位线并且被配置为接收位线地址信号并且解码位线地址信号以锁存所选择的位线，其中位线解码器包括被配置为锁存所选位线的位线锁存器。

16. 发明授权

US5768193A Bit-refreshable method and circuit for refreshing a nonvolatile flash memory 失效
标题翻译：用于刷新非易失性闪存的位刷新方法和电路
公开(公告)号：US5768193A
公开(公告)日：1998-06-16
申请号：US745034
申请日：1996-11-07
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26 , H01L27/115 , G11C16/06
CPC分类号： G11C16/3418 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3413 , G11C16/3431 , G11C8/08 , H01L27/115 , G11C16/08 , G11C16/24 , G11C2211/5644 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： In a method and circuit for refreshing a flash memory with a memory array, data corresponding to that stored in a memory cell of the memory array is read by applying a read voltage thereto. Thereafter, an erase verify voltage lower than the read voltage is applied to the memory array, and conduction of the memory cell is sensed. Based on non-conduction of the memory cell and the data of the memory cell, the memory cell is selectively discharged to compensate for undesired charge gain. Subsequently, a program verify voltage higher than the read voltage is applied to the memory array, and conduction of the memory cell is sensed. Based on conduction of the memory cell and the data of the memory cell, the memory cell is selectively charged to compensate for undesired charge loss. A method and circuit for initiating the refresh operation automatically is also disclosed.
摘要翻译：在用存储器阵列刷新闪速存储器的方法和电路中，通过对存储器阵列的存储单元中存储的读取电压来读取对应于存储器阵列的存储单元的数据。此后，将低于读取电压的擦除验证电压施加到存储器阵列，并且感测存储器单元的导通。基于存储器单元的非导通和存储单元的数据，存储单元被选择性地放电以补偿不期望的电荷增益。随后，将高于读取电压的程序验证电压施加到存储器阵列，并且感测存储器单元的导通。基于存储器单元的传导和存储单元的数据，存储单元被选择性地充电以补偿不期望的电荷损失。还公开了一种自动启动刷新操作的方法和电路。

17. 发明授权

US5687121A Flash EEPROM worldline decoder 失效
标题翻译：闪存EEPROM世界解码器
公开(公告)号：US5687121A
公开(公告)日：1997-11-11
申请号：US645630
申请日：1996-05-14
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/10 , G11C11/56 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/34 , G11C16/00
CPC分类号： G11C8/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C16/3427 , G11C2211/5642 , G11C2216/20 , G11C8/00
摘要： A flash memory wordline decoder includes a plurality of voltage terminals to receive a plurality of voltages, a plurality of address terminals to receive a plurality of address signals, a procedure terminal to receive a procedure signal, and a plurality of output wordlines adapted to be coupled to a bank of flash transistors. The wordline decoder circuit is configured to decode the address signals and includes latches coupled to the wordlines, where the latches are configured to latch the wordlines and to provide an operational voltage on the wordline to accomplish a predetermined operation responsive to the procedure signal. Advantages of the invention include a verification with a low verification voltage such as 1 V or less for operating with a VDD supply voltage as low as 1.5 V. The decoder also reduces erase/write cycle time and improves expected lifetime of the flash memory due to reduced stress on the flash transistors within the flash memory.
摘要翻译：闪存字线解码器包括多个用于接收多个电压的电压端子，多个地址端子以接收多个地址信号，用于接收过程信号的过程终端，以及适于耦合的多个输出字线到一组闪存晶体管。字线解码器电路被配置为对地址信号进行解码并且包括耦合到字线的锁存器，其中锁存器被配置为锁存字线并且在字线上提供操作电压以响应于过程信号来完成预定操作。本发明的优点包括使用诸如1V或更低的验证电压的验证，用于以低至1.5V的VDD电源电压工作。解码器还减少了擦除/写入周期时间并且改善了闪存的预期寿命，这是由于闪存中的闪存晶体管的应力减小。

18. 发明申请

US20110170357A1 NONVOLATILE MEMORY WITH A UNIFIED CELL STRUCTURE 有权
标题翻译：具有统一细胞结构的非易失性存储器
公开(公告)号：US20110170357A1
公开(公告)日：2011-07-14
申请号：US13072281
申请日：2011-03-25
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

19. 发明申请

US20110051519A1 Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface 审中-公开
标题翻译：新型基于NAND的混合NVM设计，将NAND和NOR集成在1-die与串行接口中
公开(公告)号：US20110051519A1
公开(公告)日：2011-03-03
申请号：US12807080
申请日：2010-08-27
申请人： Peter W. Lee , Kesheng Wang , Fu-Chang Hsu
发明人： Peter W. Lee , Kesheng Wang , Fu-Chang Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/32 , G11C7/1075
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. An enable signal defines a beginning and termination of a reading or writing operation. Reading one nonvolatile memory array may be interrupted for another operation and then resumed.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在串行接口上传输。串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码启用信号定义读取或写入操作的开始和结束。读取一个非易失性存储器阵列可能被中断用于另一个操作，然后恢复。

20. 发明授权

US07289366B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
公开(公告)号：US07289366B2
公开(公告)日：2007-10-30
申请号：US11376076
申请日：2006-03-15
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

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