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11. 发明申请

US20120304091A1 SYSTEM AND METHOD FOR DISCOVERING AND PUBLISHING OF PRESENCE INFORMATION ON A NETWORK 审中-公开
标题翻译：用于发现和发布网络上现有信息的系统和方法
公开(公告)号：US20120304091A1
公开(公告)日：2012-11-29
申请号：US13567820
申请日：2012-08-06
申请人： Kevin R. Moore , Peyman Oreizy , Sean O. Blagsvedt , Melissa W. Dunn , Arvind Kumar , Marcus S.H. Harvey
发明人： Kevin R. Moore , Peyman Oreizy , Sean O. Blagsvedt , Melissa W. Dunn , Arvind Kumar , Marcus S.H. Harvey
IPC分类号： G06F3/048
CPC分类号： H04L67/24 , H04L67/18
摘要： A system and method is provided for publication and discovery of the presence of nearby users on a network. When the system is enabled, the presence of the local user is published on the network. Nearby users that also have a similar system enabled can discover the local user's presence on the network. Furthermore, the local user may discovery the presence of the other nearby users that are currently publishing their presence on the network.
摘要翻译：提供了一种系统和方法用于发布和发现网络上附近用户的存在。当系统启用时，本地用户的存在将在网络上发布。启用了类似系统的附近用户也可以发现本地用户在网络上的存在。此外，本地用户可以发现当前在网络上发布其存在的其他附近用户的存在。

12. 发明申请

US20120159652A1 APPARATUS AND METHOD TO HARDEN COMPUTER SYSTEM 有权
标题翻译：硬件计算机系统的设备和方法
公开(公告)号：US20120159652A1
公开(公告)日：2012-06-21
申请号：US13404628
申请日：2012-02-24
申请人： Naga Gurumoorthy , Arvind Kumar , Matthew J. Parker
发明人： Naga Gurumoorthy , Arvind Kumar , Matthew J. Parker
IPC分类号： G06F21/00
CPC分类号： G06F21/88 , G06F9/4401 , G06F9/44542 , G06F21/575 , G06F21/73 , G06F2221/2141
摘要： In some embodiments, a processor-based system may include a processor, the processor having a processor identification, one or more electronic components coupled to the processor, at least one of the electronic components having a component identification, and a hardware security component coupled to the processor and the electronic component. The hardware security component may include a secure non-volatile memory and a controller. The controller may be configured to receive the processor identification from the processor, receive the at least one component identification from the one or more electronic components, and determine if a boot of the processor-based system is a provisioning boot of the processor-based system. If the boot is determined to be the provisioning boot, the controller may be configured to store a security code in the secure non-volatile memory, wherein the security code is based on the processor identification and the at least one component identification. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，基于处理器的系统可以包括处理器，处理器具有处理器标识，耦合到处理器的一个或多个电子部件，具有部件识别的电子部件中的至少一个以及耦合到处理器和电子元件。硬件安全组件可以包括安全的非易失性存储器和控制器。控制器可以被配置为从处理器接收处理器标识，从一个或多个电子部件接收至少一个组件标识，并且确定基于处理器的系统的启动是否是基于处理器的系统的供应引导。如果确定引导是供应启动，则控制器可以被配置为将安全代码存储在安全非易失性存储器中，其中安全代码基于处理器标识和至少一个组件标识。公开和要求保护其他实施例。

13. 发明申请

US20120079160A1 METHOD AND SYSTEM OF ADAPTING COMMUNICATION LINKS TO LINK CONDITIONS ON A PLATFORM 有权
标题翻译：将通信链接适应于平台上的链接条件的方法和系统
公开(公告)号：US20120079160A1
公开(公告)日：2012-03-29
申请号：US12890252
申请日：2010-09-24
申请人： VENKATRAMAN IYER , Arvind Kumar , Santanu Chaudhuri , Darren S. Jue , Dennis R. Halicki
发明人： VENKATRAMAN IYER , Arvind Kumar , Santanu Chaudhuri , Darren S. Jue , Dennis R. Halicki
IPC分类号： G06F13/36
CPC分类号： G06F13/36 , G06F13/4072 , G06F13/4291 , H04L12/00 , H04L12/40052 , H04L12/4013 , H04L12/40136
摘要： A method and system to adapt communication links statically and/or dynamically to their individual link conditions on a platform. The communicatively coupled devices have logic to adapt one or more settings of a respective one or more communication links with another device based at least in part on a respective metric of received data patterns from the respective one or more communication links. The communicatively coupled devices in the platform have a back channel to allow feedback or information to be sent from one receiving device to a transmitting device in one embodiment of the invention.
摘要翻译：一种方法和系统，用于使通信链路在平台上静态和/或动态地适应其各自的链路状态。所述通信耦合设备具有至少部分地基于来自相应的一个或多个通信链路的接收数据模式的相应度量而将相应的一个或多个通信链路的一个或多个通信链路的一个或多个设置适配到另一设备的逻辑。在本发明的一个实施例中，平台中的通信耦合设备具有反向信道以允许从一个接收设备向发送设备发送反馈或信息。

14. 发明授权

US08053325B1 Body contact structures and methods of manufacturing the same 有权
标题翻译：身体接触结构及其制造方法
公开(公告)号：US08053325B1
公开(公告)日：2011-11-08
申请号：US12782320
申请日：2010-05-18
申请人： Anthony Chou , Arvind Kumar , Shreesh Narasimha
发明人： Anthony Chou , Arvind Kumar , Shreesh Narasimha
IPC分类号： H01L21/336
CPC分类号： H01L29/78615 , H01L29/66772
摘要： A body contact structure which reduce parasitic capacitance and improves body resistance of a device and methods of manufacture. The method includes forming a gate insulator material and gate electrode material on a substrate. The method further includes patterning the gate insulator material and the gate electrode material to form a gate structure having a shape with a first portion isolated from a second portion. The method further includes forming source and drain regions on sides of the first portion and a body contact at a side and under an area of the second portion, and forming an interlevel dielectric within a space that isolates the first portion from the second portion of the gate structure, and over the gate structure, source and drain regions and the body contact.
摘要翻译：减少寄生电容并改善器件的体电阻和制造方法的体接触结构。该方法包括在基板上形成栅极绝缘体材料和栅电极材料。该方法还包括图案化栅极绝缘体材料和栅电极材料以形成具有与第二部分隔离的第一部分的形状的栅极结构。该方法还包括在第一部分的侧面上形成源极和漏极区域，在第二部分的侧面和下面区域形成体接触，以及在隔离第一部分与第二部分的第二部分的空间内形成层间电介质栅极结构，以及栅极结构，源极和漏极区域以及身体接触。

15. 发明申请

US20110254059A1 STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES 有权
标题翻译：用于制造不对称装置的结构和方法
公开(公告)号：US20110254059A1
公开(公告)日：2011-10-20
申请号：US13167303
申请日：2011-06-23
申请人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
发明人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
IPC分类号： H01L29/808 , H01L21/337 , B82Y99/00
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/66545 , H01L29/66659
摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.
摘要翻译：在基板上形成多个栅极结构。每个栅极结构包括第一栅极电极和源极和漏极区域。从每个栅极结构去除第一栅电极。施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。去除第一光致抗蚀剂。施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。去除第二光致抗蚀剂。在每个栅极结构中形成替代栅电极。

16. 发明授权

US08021442B2 Process for the preparation of common salt of high purity from brines in solar salt pans 有权
标题翻译：在太阳能盐锅中从盐水制备高纯度常用盐的方法
公开(公告)号：US08021442B2
公开(公告)日：2011-09-20
申请号：US12240762
申请日：2008-09-29
申请人： Arvind Kumar , Indrajit Mukhopadhyay , Pushpito Kumar Ghosh , Vadakke Puthoor Mohandas , Jignesh Jasvantrai Shukla , Rahul Jasvantrai Sanghavi
发明人： Arvind Kumar , Indrajit Mukhopadhyay , Pushpito Kumar Ghosh , Vadakke Puthoor Mohandas , Jignesh Jasvantrai Shukla , Rahul Jasvantrai Sanghavi
IPC分类号： C01D3/00
CPC分类号： C01D3/16 , C01D3/06
摘要： The process of the invention is an improvement over the existing process of producing salt of high purity from alum-treated brine disclosed recently in the prior art. More particularly, the invention rectifies the ratio of Ca2+ to Mg2+ from a value
摘要翻译：本发明的方法是相对于现有技术中最近公开的由明矾处理的卤水生产高纯度盐的现有方法的改进。更具体地说，本发明将Ca2 +与Mg2 +的比值从值<1改为由氯碱和苏打灰工业所要求的2-3的范围内的值。改进的方法包括用HCl水溶液调节澄清盐水的pH，以便在pH6.5下进行盐结晶，而不是在7的天然pH下进行盐结晶。pH调节降低了盐中的Mg 2+杂质，同时略微提高了Ca2 +杂质在盐中，从而达到所需的比例。

17. 发明申请

US20110171792A1 BACK-GATED FULLY DEPLETED SOI TRANSISTOR 有权
标题翻译：背面放置完全绝缘的SOI晶体管
公开(公告)号：US20110171792A1
公开(公告)日：2011-07-14
申请号：US12684225
申请日：2010-01-08
申请人： Leland Chang , Brian L. Ji , Arvind Kumar , Amlan Majumdar , Katherine Saenger , Leathen Shi , Jeng-Bang Yau
发明人： Leland Chang , Brian L. Ji , Arvind Kumar , Amlan Majumdar , Katherine Saenger , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , G03F9/7084 , H01L21/26506 , H01L21/2654 , H01L21/26553 , H01L21/2658 , H01L21/6835 , H01L23/544 , H01L29/78648 , H01L2221/68318 , H01L2221/68363 , H01L2221/68377 , H01L2223/54426 , H01L2224/80006 , H01L2224/8013 , H01L2224/802 , H01L2924/01019 , H01L2924/12044 , H01L2924/13091
摘要： A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner.
摘要翻译：完全耗尽的绝缘体上半导体（FDSOI）晶体管结构包括具有有限厚度并与前栅电极对准的背栅电极。背栅极通过第一氧化物覆盖层通过离子注入掺杂剂形成在第一衬底中。在第一衬底中形成全局对准标记，以使前栅电极与背栅电极对准。全局校准标记使得能够在第一衬底上制备实质上平坦的衬底，使得第一衬底可以以可靠的方式结合到第二衬底。

18. 发明申请

US20100169968A1 PROCESSOR EXTENSIONS FOR EXECUTION OF SECURE EMBEDDED CONTAINERS 有权
标题翻译：处理器扩展用于执行安全嵌入式集装箱
公开(公告)号：US20100169968A1
公开(公告)日：2010-07-01
申请号：US12347890
申请日：2008-12-31
申请人： Vedvyas Shanbhogue , Arvind Kumar , Purushottam Goel
发明人： Vedvyas Shanbhogue , Arvind Kumar , Purushottam Goel
IPC分类号： G06F12/02 , G06F21/24 , G06F9/50
CPC分类号： G06F12/1408 , G06F9/45558 , G06F9/4812 , G06F9/5077 , G06F2009/45579 , G06F2212/1052 , H04L9/14 , H04L9/3242 , H04L63/168 , H04L2209/24 , Y02D10/22 , Y02D10/24 , Y02D10/36
摘要： Methods and apparatus relating to processor extensions for execution of secure embedded containers are described. In an embodiment, a scalable solution for manageability function is provided, e.g., for UMPC environments or otherwise where utilizing a dedicated processor or microcontroller for manageability is inappropriate or impractical. For example, in an embodiment, an OS (Operating System) or VMM (Virtual Machine Manager) Independent (generally referred to herein as “OI”) architecture involves creating one or more containers on a processor by dynamically partitioning resources (such as processor cycles, memory, devices) between the HOST OS/VMM and the OI container. Other embodiments are also described and claimed.
摘要翻译：描述与用于执行安全嵌入式容器的处理器扩展有关的方法和装置。在一个实施例中，提供了用于可管理性功能的可扩展解决方案，例如对于UMPC环境，或者其他利用专用处理器或微控制器进行可管理性是不合适或不切实际的。例如，在一个实施例中，OS（操作系统）或VMM（虚拟机管理器）独立（本文通常称为“OI”）架构涉及通过动态地划分资源（例如处理器周期）来在处理器上创建一个或多个容器，内存，设备）在HOST OS / VMM和OI容器之间。还描述和要求保护其他实施例。

19. 发明申请

US20100083365A1 Apparatus and method to harden computer system 审中-公开
公开(公告)号：US20100083365A1
公开(公告)日：2010-04-01
申请号：US12587825
申请日：2009-10-14
申请人： Naga Gurumoorthy , Arvind Kumar , Matthew J. Parker
发明人： Naga Gurumoorthy , Arvind Kumar , Matthew J. Parker
IPC分类号： G06F21/00 , G06F9/24
CPC分类号： G06F21/575
摘要： In some embodiments, a processor-based system may include a processor, the processor having a processor identification, one or more electronic components coupled to the processor, at least one of the electronic components having a component identification, and a hardware security component coupled to the processor and the electronic component. The hardware security component may include a secure non-volatile memory and a controller. The controller may be configured to receive the processor identification from the processor, receive the at least one component identification from the one or more electronic components, and determine if a boot of the processor-based system is a provisioning boot of the processor-based system. If the boot is determined to be the provisioning boot, the controller may be configured to store a security code in the secure non-volatile memory, wherein the security code is based on the processor identification and the at least one component identification. Other embodiments are disclosed and claimed.

20. 发明申请

US20090302386A1 SOI TRANSISTOR HAVING A CARRIER RECOMBINATION STRUCTURE IN A BODY 失效
标题翻译：具有体内载体重构结构的SOI晶体管
公开(公告)号：US20090302386A1
公开(公告)日：2009-12-10
申请号：US12133686
申请日：2008-06-05
申请人： Anthony I. Chou , Andres Bryant , Arvind Kumar , Shreesh Narasimha
发明人： Anthony I. Chou , Andres Bryant , Arvind Kumar , Shreesh Narasimha
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/78603 , H01L29/78612
摘要： A top semiconductor layer is formed with two different thicknesses such that a step is formed underneath a body region of a semiconductor-on-insulator (SOI) field effect transistor at the interface between a top semiconductor layer and an underlying buried insulator layer. The interface and the accompanying interfacial defects in the body region provide recombination centers, which increase the recombination rate between the holes and electrons in the body region. Optionally, a spacer portion, comprising a material that functions as recombination centers, is formed on sidewalls of the step to provide an enhanced recombination rate between holes and electrons in the body region, which increases the bipolar breakdown voltage of a SOI field effect transistor.
摘要翻译：顶部半导体层形成有两个不同的厚度，使得在顶部半导体层和下面的掩埋绝缘体层之间的界面处在绝缘体上半导体（SOI）场效应晶体管的体区之下形成台阶。身体区域中的界面和伴随的界面缺陷提供了复合中心，这增加了身体区域中的空穴和电子之间的复合速率。任选地，包括作为复合中心的材料的间隔物部分形成在台阶的侧壁上，以在体区中的空穴和电子之间提供增强的复合率，这增加了SOI场效应晶体管的双极击穿电压。

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