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1. 发明申请

US20120079160A1 METHOD AND SYSTEM OF ADAPTING COMMUNICATION LINKS TO LINK CONDITIONS ON A PLATFORM 有权
标题翻译：将通信链接适应于平台上的链接条件的方法和系统
公开(公告)号：US20120079160A1
公开(公告)日：2012-03-29
申请号：US12890252
申请日：2010-09-24
申请人： VENKATRAMAN IYER , Arvind Kumar , Santanu Chaudhuri , Darren S. Jue , Dennis R. Halicki
发明人： VENKATRAMAN IYER , Arvind Kumar , Santanu Chaudhuri , Darren S. Jue , Dennis R. Halicki
IPC分类号： G06F13/36
CPC分类号： G06F13/36 , G06F13/4072 , G06F13/4291 , H04L12/00 , H04L12/40052 , H04L12/4013 , H04L12/40136
摘要： A method and system to adapt communication links statically and/or dynamically to their individual link conditions on a platform. The communicatively coupled devices have logic to adapt one or more settings of a respective one or more communication links with another device based at least in part on a respective metric of received data patterns from the respective one or more communication links. The communicatively coupled devices in the platform have a back channel to allow feedback or information to be sent from one receiving device to a transmitting device in one embodiment of the invention.
摘要翻译：一种方法和系统，用于使通信链路在平台上静态和/或动态地适应其各自的链路状态。所述通信耦合设备具有至少部分地基于来自相应的一个或多个通信链路的接收数据模式的相应度量而将相应的一个或多个通信链路的一个或多个通信链路的一个或多个设置适配到另一设备的逻辑。在本发明的一个实施例中，平台中的通信耦合设备具有反向信道以允许从一个接收设备向发送设备发送反馈或信息。

2. 发明申请

US20130007491A1 ENHANCED INTERCONNECT LINK WIDTH MODULATION FOR POWER SAVINGS 有权
标题翻译：增强的互联互连宽带调节功率节省
公开(公告)号：US20130007491A1
公开(公告)日：2013-01-03
申请号：US13175794
申请日：2011-07-01
申请人： VENKATRAMAN IYER , ROBERT G. BLANKENSHIP , DENNIS R. HALICKI
发明人： VENKATRAMAN IYER , ROBERT G. BLANKENSHIP , DENNIS R. HALICKI
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3206 , G06F1/3243 , Y02D10/152 , Y02D10/171
摘要： Methods and apparatus relating to enhanced interconnect link width modulation for power savings are described. In one embodiment, the width of a link is modified from a first width to a second width in response to a power management flit, while non-idle flits continue to be transmitted over the link after transmission of the power management flit. Other embodiments are also disclosed and claimed.
摘要翻译：描述了与增强的互连链路宽度调制相关的功率节省的方法和装置。在一个实施例中，响应于电源管理飞行，链路的宽度从第一宽度修改为第二宽度，而在发送电源管理飞行之后，非空闲飞行继续在链路上传输。还公开并要求保护其他实施例。

3. 发明申请

US20140281071A1 OPTICAL MEMORY EXTENSION ARCHITECTURE 审中-公开
标题翻译：光学存储器扩展架构
公开(公告)号：US20140281071A1
公开(公告)日：2014-09-18
申请号：US13844083
申请日：2013-03-15
申请人： JIANPING JANE XU , DONALD FAW , VENKATRAMAN IYER
发明人： JIANPING JANE XU , DONALD FAW , VENKATRAMAN IYER
IPC分类号： G06F13/42
CPC分类号： G06F13/42 , G06F13/4045
摘要： An optical memory extension architecture. A first electrical logic circuit on a first die communicates data according to a packetized, point-to-point interconnect protocol at a full data rate. A first gasket circuit is coupled to receive the data from the first electrical logic circuit. The first gasket circuit causes the data to be converted to an optical format to be transmitted at a rate that is at least double the full data rate. A second gasket circuit is coupled to receive the data in the optical format from the first gasket circuit. The second gasket circuit causes the data to be converted to an electrical format conforming to the packetized, point-to-point interconnect protocol. A second electrical logic circuit on a second die is coupled to receive the data from the first electrical logic circuit through the first gasket circuit and the second gasket circuit.
摘要翻译：光学存储器扩展架构。第一芯片上的第一电逻辑电路以全数据速率根据打包的点对点互连协议传送数据。第一垫片电路被耦合以从第一电逻辑电路接收数据。第一垫片电路使得数据被转换成以至少是全数据速率的两倍的速率传输的光学格式。第二垫片电路被耦合以从第一垫片电路接收光学格式的数据。第二垫片电路使得数据被转换成符合分组化的点对点互连协议的电格式。第二管芯上的第二电逻辑电路被耦合以通过第一衬垫电路和第二衬垫电路从第一电逻辑电路接收数据。

4. 发明申请

US20130007502A1 REPURPOSING DATA LANE AS CLOCK LANE BY MIGRATING TO REDUCED SPEED LINK OPERATION 有权
标题翻译：通过移动减少速度链路操作，将数据路由作为时钟路由
公开(公告)号：US20130007502A1
公开(公告)日：2013-01-03
申请号：US13175798
申请日：2011-07-01
申请人： VENKATRAMAN IYER , ROBERT G. BLANKENSHIP , ALLEN J. BAUM
发明人： VENKATRAMAN IYER , ROBERT G. BLANKENSHIP , ALLEN J. BAUM
IPC分类号： G06F11/20
CPC分类号： G06F11/1428 , G06F11/1423 , G06F11/1604
摘要： Methods and apparatus relating to repurposing a data lane as a clock lane by migrating to reduced speed link operation are described. In one embodiment, speed of a link is reduced upon detection of failure on a clock lane of the link and one of a plurality of data lanes of a link is repurposed as a replacement clock lane. Other embodiments are also disclosed and claimed.
摘要翻译：描述通过迁移到降低速度链接操作将与数据通道重新设置为时钟通道有关的方法和装置。在一个实施例中，在检测到链路的时钟通道上的故障并且链路的多个数据通道中的一个被重新利用作为替换时钟通道时，链路的速度被降低。还公开并要求保护其他实施例。

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