专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20180357178A1 ACCESS CONTROL 审中-公开
公开(公告)号：US20180357178A1
公开(公告)日：2018-12-13
申请号：US15620017
申请日：2017-06-12
申请人： ARM LIMITED
发明人： Bruce James MATHEWSON , Phanindra Kumar MANNAVA , Matthew Lucien EVANS , Paul Gilbert MEYER , Andrew Brookfield SWAINE
IPC分类号： G06F12/1036 , G06F12/0802 , G06F12/14 , G06F13/16
CPC分类号： G06F12/1036 , G06F12/0802 , G06F12/1425 , G06F13/1668
摘要： Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.

12. 发明申请

US20180225209A1 READ-WITH OVERRIDABLE-INVALIDATE TRANSACTION 审中-公开
公开(公告)号：US20180225209A1
公开(公告)日：2018-08-09
申请号：US15427320
申请日：2017-02-08
申请人： ARM Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Jamshed JALAL , Mark David WERKHEISER
IPC分类号： G06F12/0831 , G06F12/0804 , G06F12/0808 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0891 , G06F12/0897
CPC分类号： G06F12/0831 , G06F12/0804 , G06F12/0808 , G06F12/0811 , G06F12/0833 , G06F12/084 , G06F12/0842 , G06F12/0891 , G06F12/0897 , G06F2212/1016 , G06F2212/302 , G06F2212/6042
摘要： A system comprises a number of master devices and an interconnect for managing coherency between the master devices. In response to a read-with-overridable-invalidate transaction received by the interconnect from a requesting master device requesting that target data associated with a target address is provided to the requesting master device, when target data associated with the target address is stored by a cache, the interconnect issues a snoop request to said cache triggering invalidation of the target data from the cache except when the interconnect or cache determines to override the invalidation and retain the target data in the cache. This enables greater efficiency in cache usage since data which the requesting master considers is unlikely to be needed again can be invalidated from caches located outside the master device itself.

13. 发明申请

US20140040516A1 BARRIER TRANSACTIONS IN INTERCONNECTS 有权
标题翻译：互连中的障碍交易
公开(公告)号：US20140040516A1
公开(公告)日：2014-02-06
申请号：US13960128
申请日：2013-08-06
申请人： ARM LIMITED
发明人： Peter Andrew RIOCREUX , Bruce James MATHEWSON , Christopher William LAYCOCK , Richard Roy GRISENTHWAITE
IPC分类号： G06F13/362
CPC分类号： G06F13/362 , G06F13/1621 , G06F13/1689 , G06F13/364
摘要： Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.
摘要翻译：互连电路被配置为提供数据路由，至少一个发起者设备可经由该路由访问至少一个接收者设备。所述电路包括：用于从至少一个发起者设备接收交易请求的至少一个输入; 用于向所述至少一个接收设备输出交易请求的至少一个输出; 以及用于在至少一个输入和至少一个输出之间传送事务请求的至少一个路径。还包括用于将接收到的交易请求从至少一个输入路由到至少一个输出的控制电路，并且响应于屏障事务请求以维持关于业务流内的所述屏障事务请求的至少一些交易请求的排序沿着所述至少一条路径中的一条通过的请求。阻塞事务请求包括要保持其顺序的事务请求的指示符。

14. 发明申请

US20220283972A1 TECHNIQUE FOR HANDLING PROTOCOL CONVERSION 有权
公开(公告)号：US20220283972A1
公开(公告)日：2022-09-08
申请号：US17189781
申请日：2021-03-02
申请人： Arm Limited
发明人： Ashok Kumar TUMMALA , Jamshed JALAL , Antony John HARRIS , Jeffrey Carl DEFILIPPI , Anitha KONA , Bruce James MATHEWSON
IPC分类号： G06F13/38 , G06F13/40
摘要： An apparatus and method are provided for handling protocol conversion. The apparatus has interconnect circuitry for routing messages between components coupled to the interconnect circuitry in a manner that conforms to a first communication protocol. Protocol conversion circuitry is coupled between the interconnect circuitry and an external communication path, for converting messages between the first communication protocol and a second communication protocol that has a layered architecture comprising multiple layers. The protocol conversion circuitry has a gateway component forming one of the components coupled to the interconnect circuitry, and a controller coupled with the gateway component and used to control connection with the external communication path. For a selected layer of the multiple layers, the protocol conversion circuitry provides, within the gateway component, upper selected layer circuitry to implement a first portion of functionality of the selected layer, where the first portion comprises at least protocol dependent functionality of the selected layer. It also provides, within the controller, lower selected layer circuitry to implement a remaining portion of the functionality of the selected layer, the remaining portion comprising only protocol independent functionality of the selected layer.

15. 发明申请

US20200133865A1 CACHE MAINTENANCE OPERATIONS IN A DATA PROCESSING SYSTEM 审中-公开
公开(公告)号：US20200133865A1
公开(公告)日：2020-04-30
申请号：US16173213
申请日：2018-10-29
申请人： Arm Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Jamshed JALAL , Paul Gilbert MEYER
IPC分类号： G06F12/0868 , G06F12/0871 , G06F12/1009 , G06F9/52 , G06F3/06
摘要： An interconnect system and method of operating the system are disclosed. A master device has access to a cache and a slave device has an associated data storage device for long-term storage of data items. The master device can initiate a cache maintenance operation in the interconnect system with respect to a data item temporarily stored in the cache causing action to be taken by the slave device with respect to storage of the data item in the data storage device. For long latency operations the master device can issue a separated cache maintenance request specifying the data item and the slave device. In response an intermediate device signals an acknowledgment response indicating that it has taken on responsibility for completion of the cache maintenance operation and issues the separated cache maintenance request to the slave device. The slave device signals the acknowledgement response to the intermediate device and on completion of the cache maintenance operation with respect to the data item stored in the data storage device signals a completion response to the master device.

16. 发明申请

US20180225206A1 READ TRANSACTION TRACKER LIFETIMES IN A COHERENT INTERCONNECT SYSTEM 审中-公开
公开(公告)号：US20180225206A1
公开(公告)日：2018-08-09
申请号：US15427435
申请日：2017-02-08
申请人： ARM Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Jamshed JALAL , Tushar P RINGE
IPC分类号： G06F12/0815 , G06F12/1081
摘要： Apparatus and a corresponding method of operating the apparatus, in a coherent interconnect system comprising a requesting master device and a data-storing slave device, are provided. The apparatus maintains records of coherency protocol transactions received from the requesting master device whilst completion of the coherency protocol transactions are pending and is responsive to reception of a read transaction from the requesting master device for a data item stored in the data-storing slave device to issue a direct memory transfer request to the data-storing slave device. A read acknowledgement trigger is added to the direct memory transfer request and in response to reception of a read acknowledgement signal from the data-storing slave device a record created by reception of the read transaction is updated corresponding to completion of the direct memory transfer request. The lifetime that the apparatus needs to maintain the record is thus reduced, despite the read transaction being satisfied by a direct memory transfer. A corresponding data-storing slave device and method of operating the data-storing slave device are also provided.

17. 发明申请

US20180173660A1 DATA PROCESSING 审中-公开
公开(公告)号：US20180173660A1
公开(公告)日：2018-06-21
申请号：US15384688
申请日：2016-12-20
申请人： ARM Limited
发明人： Guanghui GENG , Andrew David TUNE , Daniel Adam SARA , Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Jamshed JALAL
IPC分类号： G06F13/364 , G06F13/42 , G06F13/40 , G06F12/0888 , G06F12/0815
CPC分类号： G06F13/364 , G06F12/0815 , G06F12/0888 , G06F13/404 , G06F13/4282 , G06F2212/6046 , G06F2212/621
摘要： A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

18. 发明申请

US20180032435A1 CACHE MAINTENANCE INSTRUCTION 审中-公开
公开(公告)号：US20180032435A1
公开(公告)日：2018-02-01
申请号：US15549284
申请日：2016-01-12
申请人： ARM LIMITED
发明人： Jason PARKER , Bruce James MATHEWSON , Matthew Lucien EVANS
IPC分类号： G06F12/0831 , G06F12/1009
CPC分类号： G06F12/0833 , G06F12/0831 , G06F12/10 , G06F12/1009 , G06F2212/1016 , G06F2212/655 , Y02D10/13
摘要： An apparatus (2) comprises processing circuitry (4) for performing data processing in response to instructions. The processing circuitry (4) supports a cache maintenance instruction (50) specifying a virtual page address (52) identifying a virtual page of a virtual address space. In response to the cache maintenance instruction, the processing circuitry (4) triggers at least one cache (18, 20, 22) to perform a cache maintenance operation on one or more cache lines for which a physical address of the data stored by the cache line is within a physical page that corresponds to the virtual page identified by the virtual page address provided by the cache maintenance instruction.

19. 发明申请

US20210103524A1 CIRCUITRY AND METHODS 有权
公开(公告)号：US20210103524A1
公开(公告)日：2021-04-08
申请号：US16595863
申请日：2019-10-08
申请人： Arm Limited
发明人： Bruce James MATHEWSON , Phanindra Kumar MANNAVA , Jamshed JALAL , Klas Magnus BRUCE , Andrew John TURNER
IPC分类号： G06F12/0815 , G06F9/52
摘要： Circuitry comprises a set of two or more data handling nodes each having respective storage circuitry to hold data; and a home node to serialise data access operations and to control coherency amongst data held by the one or more data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; in which: a requesting node of the set of data handling nodes is configured to communicate a request to the home node for exclusive access to a given instance of data at a given memory address; and the home node is configured, in response to the request, to communicate information to other data handling nodes of the set of data handling nodes to control handling, by those other data handling nodes, of any further instances of the data at the given memory address which are held by those other data handling nodes.

20. 发明申请

US20200050568A1 DATA PROCESSING 审中-公开
公开(公告)号：US20200050568A1
公开(公告)日：2020-02-13
申请号：US16659762
申请日：2019-10-22
申请人： Arm Limited
发明人： Guanghui GENG , Andrew David TUNE , Daniel Adam SARA , Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Jamshed JALAL
IPC分类号： G06F13/364 , G06F12/0815 , G06F12/0888 , G06F13/40 , G06F13/42
摘要： A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式