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1. 发明申请

US20190342034A1 TRANSFER PROTOCOL IN A DATA PROCESSING NETWORK 审中-公开
公开(公告)号：US20190342034A1
公开(公告)日：2019-11-07
申请号：US16027864
申请日：2018-07-05
申请人： Arm Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Jamshed JALAL , Tushar P. RINGE
IPC分类号： H04L1/16 , H04L29/08
摘要： In a data processing network comprising one or more Request Nodes and a Home Node coupled via a coherent interconnect, a Request Node requests data from the Home Node. The requested data is sent, via the interconnect, to the Request Node in a plurality of data beats, where a first data beat of the plurality of data beats is received at a first time and a last data beat is received at a second time. Responsive to receiving the first data beat, the Request Node sends an acknowledgement message to the Home Node. Upon receipt of the acknowledgement message, the Home Node frees resources allocated to the read transaction. In addition, the Home Node is configured to allow snoop requests for the data to the Request Node to be sent to the Request Node before all beats of the requested data have been received by the Request Node.

2. 发明申请

US20180225216A1 DATA PROCESSING 审中-公开
公开(公告)号：US20180225216A1
公开(公告)日：2018-08-09
申请号：US15427421
申请日：2017-02-08
申请人： ARM Limited
发明人： Michael FILIPPO , Jamshed JALAL , Klas Magnus BRUCE , Alex James WAUGH , Geoffray LACOURBA , Paul Gilbert MEYER , Bruce James MATHEWSON , Phanindra Kumar MANNAVA
IPC分类号： G06F12/0862 , G06F15/78
CPC分类号： G06F12/0862 , G06F11/34 , G06F12/0811 , G06F12/0833 , G06F15/7825 , G06F2212/502 , G06F2212/507
摘要： Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.

3. 发明申请

US20180225214A1 CACHE CONTENT MANAGEMENT 审中-公开
公开(公告)号：US20180225214A1
公开(公告)日：2018-08-09
申请号：US15427459
申请日：2017-02-08
申请人： ARM Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Jamshed JALAL , Klas Magnus BRUCE , Michael FILIPPO , Paul Gilbert MEYER , Alex James WAUGH , Geoffray Matthieu LACOURBA
IPC分类号： G06F12/0831 , G06F9/46
CPC分类号： G06F12/0835 , G06F12/0808 , G06F2212/1024 , G06F2212/621
摘要： Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.

4. 发明申请

US20210103543A1 NON-FORWARDABLE TRANSFERS 有权
公开(公告)号：US20210103543A1
公开(公告)日：2021-04-08
申请号：US16593127
申请日：2019-10-04
申请人： Arm Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Klas Magnus BRUCE , Damien Guillaume Pierre PAYET , Jamshed JALAL , Alex James WAUGH
IPC分类号： G06F13/40 , G06F13/16 , G06F12/0815
摘要： An apparatus to is provided, to be used with an interconnect comprising a home node. The apparatus includes general-purpose storage circuitry and specialised storage circuitry. Transfer circuitry performs a non-forwardable transfer of a data item from the general-purpose storage circuitry to the specialised storage circuitry. Transmit circuitry transmits an offer to the home node, at a time of the non-forwardable transfer, to transfer the data item to the home node. The apparatus is inhibited from forwarding the data item from the specialised storage circuitry to the home node.

5. 发明申请

US20210103493A1 MEMORY INTERFACE HAVING DATA SIGNAL PATH AND TAG SIGNAL PATH 有权
公开(公告)号：US20210103493A1
公开(公告)日：2021-04-08
申请号：US16594223
申请日：2019-10-07
申请人： Arm Limited
发明人： Bruce James MATHEWSON , Phanindra Kumar MANNAVA , Michael Andrew CAMPBELL , Alexander Alfred HORNUNG , Alex James WAUGH , Klas Magnus BRUCE , Richard Roy GRISENTHWAITE
IPC分类号： G06F11/10 , G06F11/30 , G11C29/18
摘要： A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

6. 发明申请

US20210103460A1 WRITING ZERO DATA 有权
公开(公告)号：US20210103460A1
公开(公告)日：2021-04-08
申请号：US16592979
申请日：2019-10-04
申请人： Arm Limited
发明人： Jamshed JALAL , Mark David WERKHEISER , Phanindra Kumar MANNAVA , Bruce James MATHEWSON
IPC分类号： G06F9/46 , G06F9/455 , G06F9/38 , G06F13/40 , G06F12/10 , G06F12/0891
摘要： Apparatuses, methods of operating apparatuses, interconnects for connecting apparatuses to one another, and methods of operating the interconnects are disclosed. A master apparatus can issue an individual all-zero-data write transaction specifying a data storage location to the interconnect, which conveys the individual all-zero-data write transaction to a target device which writes all-zero-data at the data storage location. No write data is conveyed with the individual all-zero-data write transaction, so that the individual all-zero-data write transaction may be used to clear the data storage location without adding to congestion of a write data channel in the interconnect.

7. 发明申请

US20180227382A1 FORWARDING RESPONSES TO SNOOP REQUESTS 审中-公开
公开(公告)号：US20180227382A1
公开(公告)日：2018-08-09
申请号：US15427384
申请日：2017-02-08
申请人： ARM Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Jamshed JALAL , Klas Magnus BRUCE
IPC分类号： H04L29/08 , G06F12/0831
CPC分类号： H04L67/2814 , G06F12/0831 , G06F2212/621 , H04L67/10 , H04L67/2842
摘要： A data processing apparatus is provided, which includes receiving circuitry to receive a snoop request in respect of requested data on behalf of a requesting node. The snoop request includes an indication as to whether forwarding is to occur. Transmitting circuitry transmits a response to the snoop request and cache circuitry caches at least one data value. When forwarding is to occur and the at least one data value includes the requested data, the response includes the requested data and the transmitting circuitry transmits the response to the requesting node.

8. 发明申请

US20180225047A1 COMPARE-AND-SWAP TRANSACTION 审中-公开
公开(公告)号：US20180225047A1
公开(公告)日：2018-08-09
申请号：US15427335
申请日：2017-02-08
申请人： ARM Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Klas Magnus BRUCE , Geoffray Matthieu LACOURBA
IPC分类号： G06F3/06 , G06F12/06
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0683 , G06F9/52 , G06F9/526 , G06F12/06 , G06F2212/1024
摘要： A compare and swap transaction can be issued by a master device to request a processing unit to select whether to write a swap data value to a storage location corresponding to a target address in dependence on whether a compare data value matches a target data value read from the storage location. The compare and swap data values are transported within a data field of the compare and swap transaction. The compare data value is packed into a first region of the data field in dependence of an offset portion of the target address and having a position within the data field corresponding to the position of the target data value within the storage location. This reduces latency and circuitry required at the processing unit for handling the compare and swap transaction.

9. 发明申请

US20210103525A1 APPARATUS AND METHOD FOR HANDLING CACHE MAINTENANCE OPERATIONS 有权
公开(公告)号：US20210103525A1
公开(公告)日：2021-04-08
申请号：US16591827
申请日：2019-10-03
申请人： Arm Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Jamshed JALAL
IPC分类号： G06F12/0897 , G06F12/0871 , G06F12/0868
摘要： An apparatus and method are provided for handling cache maintenance operations. The apparatus has a plurality of requester elements for issuing requests and at least one completer element for processing such requests. A cache hierarchy is provided having a plurality of levels of cache to store cached copies of data associated with addresses in memory. A requester element may be arranged to issue a cache maintenance operation request specifying a memory address range in order to cause a block of data associated with the specified memory address range to be pushed through at least one level of the cache hierarchy to a determined visibility point in order to make that block of data visible to one or more other requester elements. The given requester element may be arranged to detect when there is a need to issue a write request prior to the cache maintenance operation request in order to cause a write operation to be performed in respect of data within the specified memory address range, and in that event to generate a combined write and cache maintenance operation request to be issued instead of the write request and a subsequent cache maintenance operation request. A recipient completer element that receives the combined write and cache maintenance operation request may then be arranged to initiate processing of the cache maintenance operation required by the combined write and cache maintenance operation request without waiting for the write operation to complete. This can significantly reduce latency in the handling of cache maintenance operations, and can provide for reduced bandwidth utilisation.

10. 发明申请

US20190340138A1 SEPARATING COMPLETION AND DATA RESPONSES FOR HIGHER READ THROUGHPUT AND LOWER LINK UTILIZATION IN A DATA PROCESSING NETWORK 审中-公开
公开(公告)号：US20190340138A1
公开(公告)日：2019-11-07
申请号：US16027929
申请日：2018-07-05
申请人： Arm Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Jamshed JALAL , Tushar P. RINGE , Klas Magnus BRUCE
IPC分类号： G06F13/16 , G06F12/0813 , G06F12/0815
摘要： In a data processing network comprising a Request, Home and Slave Nodes coupled via a coherent interconnect, a Home Node performs a read transaction in response to a read request from a Request Node. In a first embodiment, the transaction is terminated in the Home Node upon receipt of a read receipt from a Slave Node, acknowledging a read request from the Home Node. In a second embodiment, the Home Node sends a message to the Request Node indicating that a read transaction has been ordered in the Home Node and further indicating that data for the read transaction is provided in a separate data response. The transaction is terminated in the Home Node upon receipt of an acknowledge from the Request Node of this message. In this manner, the transaction is terminated in the Home Node without waiting for acknowledgement from the Request Node of completion of the transaction.

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