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1. 发明申请

US20180357178A1 ACCESS CONTROL 审中-公开
公开(公告)号：US20180357178A1
公开(公告)日：2018-12-13
申请号：US15620017
申请日：2017-06-12
申请人： ARM LIMITED
发明人： Bruce James MATHEWSON , Phanindra Kumar MANNAVA , Matthew Lucien EVANS , Paul Gilbert MEYER , Andrew Brookfield SWAINE
IPC分类号： G06F12/1036 , G06F12/0802 , G06F12/14 , G06F13/16
CPC分类号： G06F12/1036 , G06F12/0802 , G06F12/1425 , G06F13/1668
摘要： Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.

2. 发明申请

US20200167284A1 APPARATUS AND METHOD FOR PROCESSING AN OWNERSHIP UPGRADE REQUEST FOR CACHED DATA THAT IS ISSUED IN RELATION TO A CONDITIONAL STORE OPERATION 审中-公开
公开(公告)号：US20200167284A1
公开(公告)日：2020-05-28
申请号：US16202171
申请日：2018-11-28
申请人： Arm Limited
发明人： Jamshed JALAL , Mark David WERKHEISER , Michael FILIPPO , Klas Magnus BRUCE , Paul Gilbert MEYER
IPC分类号： G06F12/0815 , G06F13/16
摘要： An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units. The coherent interconnect may receive, from a first processing unit having an associated cache storage, an ownership upgrade request specifying a target memory address, the ownership upgrade request indicating that a copy of data at the target memory address, as held in a shared state in the first processing unit's associated cache storage at a time the ownership upgrade request was issued, is required to have its state changed from the shared state to a unique state prior to the first processing circuitry performing a write operation to the data. The coherent interconnect is arranged to process the ownership upgrade request by referencing the snoop unit in order to determine whether the first processing unit's associated cache storage is identified as still holding a copy of the data at the target memory address at a time the ownership upgrade request is processed. In that event, a pass condition is identified for the ownership upgrade request independent of information held by the contention management circuitry for the target memory address.

3. 发明申请

US20180225216A1 DATA PROCESSING 审中-公开
公开(公告)号：US20180225216A1
公开(公告)日：2018-08-09
申请号：US15427421
申请日：2017-02-08
申请人： ARM Limited
发明人： Michael FILIPPO , Jamshed JALAL , Klas Magnus BRUCE , Alex James WAUGH , Geoffray LACOURBA , Paul Gilbert MEYER , Bruce James MATHEWSON , Phanindra Kumar MANNAVA
IPC分类号： G06F12/0862 , G06F15/78
CPC分类号： G06F12/0862 , G06F11/34 , G06F12/0811 , G06F12/0833 , G06F15/7825 , G06F2212/502 , G06F2212/507
摘要： Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.

4. 发明申请

US20180225214A1 CACHE CONTENT MANAGEMENT 审中-公开
公开(公告)号：US20180225214A1
公开(公告)日：2018-08-09
申请号：US15427459
申请日：2017-02-08
申请人： ARM Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Jamshed JALAL , Klas Magnus BRUCE , Michael FILIPPO , Paul Gilbert MEYER , Alex James WAUGH , Geoffray Matthieu LACOURBA
IPC分类号： G06F12/0831 , G06F9/46
CPC分类号： G06F12/0835 , G06F12/0808 , G06F2212/1024 , G06F2212/621
摘要： Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.

5. 发明申请

US20200133865A1 CACHE MAINTENANCE OPERATIONS IN A DATA PROCESSING SYSTEM 审中-公开
公开(公告)号：US20200133865A1
公开(公告)日：2020-04-30
申请号：US16173213
申请日：2018-10-29
申请人： Arm Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Jamshed JALAL , Paul Gilbert MEYER
IPC分类号： G06F12/0868 , G06F12/0871 , G06F12/1009 , G06F9/52 , G06F3/06
摘要： An interconnect system and method of operating the system are disclosed. A master device has access to a cache and a slave device has an associated data storage device for long-term storage of data items. The master device can initiate a cache maintenance operation in the interconnect system with respect to a data item temporarily stored in the cache causing action to be taken by the slave device with respect to storage of the data item in the data storage device. For long latency operations the master device can issue a separated cache maintenance request specifying the data item and the slave device. In response an intermediate device signals an acknowledgment response indicating that it has taken on responsibility for completion of the cache maintenance operation and issues the separated cache maintenance request to the slave device. The slave device signals the acknowledgement response to the intermediate device and on completion of the cache maintenance operation with respect to the data item stored in the data storage device signals a completion response to the master device.

6. 发明申请

US20170168876A1 OPTIMIZED STREAMING IN AN UN-ORDERED INTERCONNECT 有权
公开(公告)号：US20170168876A1
公开(公告)日：2017-06-15
申请号：US15296283
申请日：2016-10-18
申请人： ARM Limited
发明人： Ashok Kumar TUMMALA , Jamshed JALAL , Paul Gilbert MEYER , Dimitrios KASERIDIS
IPC分类号： G06F9/52 , G06F9/50
摘要： A method, system, and device provide for the streaming of ordered requests from one or more Senders to one or more Receivers over an un-ordered interconnect while mitigating structural deadlock conditions.

7. 发明申请

US20180225232A1 DATA PROCESSING 审中-公开
公开(公告)号：US20180225232A1
公开(公告)日：2018-08-09
申请号：US15427391
申请日：2017-02-08
申请人： ARM Limited
发明人： Michael FILIPPO , Jamshed JALAL , Klas Magnus BRUCE , Paul Gilbert MEYER , David Joseph HAWKINS , Phanindra Kumar MANNAVA , Joseph Michael PUSDESRIS
IPC分类号： G06F13/16 , G06F13/364 , G06F12/0864 , G06F13/42 , G06F13/40
CPC分类号： G06F13/1642 , G06F12/0833 , G06F12/0844 , G06F12/0864 , G06F13/1668 , G06F13/364 , G06F13/404 , G06F13/4282 , G06F2212/6032 , G06F2212/621
摘要： A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.

8. 发明申请

US20170168954A1 SYSTEM ADDRESS MAP FOR HASHING WITHIN A CHIP AND BETWEEN CHIPS 审中-公开
公开(公告)号：US20170168954A1
公开(公告)日：2017-06-15
申请号：US14965214
申请日：2015-12-10
申请人： ARM Limited
发明人： Paul Gilbert MEYER , Gurunath RAMAGIRI
IPC分类号： G06F12/10 , G06F13/40 , G06F3/06
CPC分类号： G06F12/1018 , G06F3/0604 , G06F3/0659 , G06F3/067 , G06F13/4068 , G06F2212/657
摘要： A system and method for accessing on-chip and off-chip memory in an integrated circuit data processing system. The system includes a number of nodes connected by an interconnect and also includes system address map logic in which a node register table is accessed using a hash function of the memory address to be accessed. A node identifier stored in a register of the node register table is an identifier of a remote-connection node when the memory address is in off-chip memory addresses and an identifier of a local-connection node when the memory address is in the off-chip memory. Transaction requests are routed using the node identifier selected using the hash function.

9. 发明申请

US20170168548A1 SEGREGATED POWER STATE CONTROL IN A DISTRIBUTED CACHE SYSTEM 审中-公开
公开(公告)号：US20170168548A1
公开(公告)日：2017-06-15
申请号：US14965184
申请日：2015-12-10
申请人： ARM Limited
发明人： Mark David WERKHEISER , Dominic William BROWN , Ashley John CRAWFORD , Paul Gilbert MEYER
IPC分类号： G06F1/32 , G06F12/08
摘要： A method, system, and device provide for selective control in a distributed cache system of the power state of a number of receiver partitions arranged in one or more partition groups. A power control element coupled to one or more of the receiver partitions and a coherent interconnect selectively control transition from a current power state to a new power state by each receiver partition of one or more partition groups of the plurality of partition groups.

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