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11. 发明授权

US06657267B1 Semiconductor device and fabrication technique using a high-K liner for spacer etch stop 有权
标题翻译：半导体器件和使用高K衬垫进行间隔蚀刻停止的制造技术
公开(公告)号：US06657267B1
公开(公告)日：2003-12-02
申请号：US10163930
申请日：2002-06-06
申请人： Qi Xiang , Olov Karlsson , HaiHong Wang , Bin Yu
发明人： Qi Xiang , Olov Karlsson , HaiHong Wang , Bin Yu
IPC分类号： H01L2976
CPC分类号： H01L29/517 , H01L21/2652 , H01L21/28167 , H01L21/28194 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/6656 , H01L29/6659
摘要： A semiconductor device and method of fabrication are disclosed. The semiconductor device includes a liner composed of a high-K material. The liner has a portion separating a sidewall spacer from a gate and a portion separating the sidewall spacer from a layer of semiconductor material. The liner functions as an etch stop during formation of the sidewall spacer. The liner is removable by an etch process that has substantially no reaction with an isolation region formed in the layer of semiconductor material.
摘要翻译：公开了半导体器件和制造方法。半导体器件包括由高K材料构成的衬垫。衬套具有将侧壁间隔物与栅极分离的部分和将侧壁间隔物与半导体材料层分离的部分。衬垫在形成侧壁间隔物期间用作蚀刻停止。衬里可以通过蚀刻工艺去除，该蚀刻工艺基本上不与半导体材料层中形成的隔离区域发生反应。

12. 发明授权

US06528858B1 MOSFETs with differing gate dielectrics and method of formation 有权
标题翻译：具有不同栅极电介质的MOSFET和形成方法
公开(公告)号：US06528858B1
公开(公告)日：2003-03-04
申请号：US10044892
申请日：2002-01-11
申请人： Bin Yu , Qi Xiang , Olov Karlsson , HaiHong Wang , Zoran Krivokapic
发明人： Bin Yu , Qi Xiang , Olov Karlsson , HaiHong Wang , Zoran Krivokapic
IPC分类号： H01L2902
CPC分类号： H01L29/513 , H01L21/28167 , H01L21/28194 , H01L21/76264 , H01L21/823857 , H01L21/84 , H01L27/1203 , H01L29/517 , H01L29/518
摘要： A semiconductor wafer including an NMOS device and a PMOS device. The NMOS device is formed to have a high-K gate dielectric and the PMOS device is formed to have a standard-K gate dielectric. A method of forming the NMOS device and the PMOS device is also disclosed.
摘要翻译：一种包括NMOS器件和PMOS器件的半导体晶片。 NMOS器件形成为具有高K栅极电介质，并且PMOS器件形成为具有标准K栅极电介质。还公开了形成NMOS器件和PMOS器件的方法。

13. 发明授权

US6162699A Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery 有权
标题翻译：用于产生有限隔离沟槽宽度结构的方法和具有围绕其周边的窄隔离沟槽的器件
公开(公告)号：US6162699A
公开(公告)日：2000-12-19
申请号：US181561
申请日：1998-10-29
申请人： Larry Wang , Nick Kepler , Olov Karlsson , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
发明人： Larry Wang , Nick Kepler , Olov Karlsson , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S438/942 , Y10S438/945
摘要： A method for effectively generating limited trench width isolation structures without incurring the susceptibility to dishing problems to produce high quality ICs employs a computer to generate data representing a trench isolation mask capable of being used to etch a limited trench width isolation structure about the perimeter of active region layers, polygate layers, and Local Interconnect (LI) layers. Once the various layers are defined using data on the computer and configured such that chip real estate is maximized, then the boundaries are combined using, for example, logical OR operators to produce data representing an overall composite layer. Once the data representing the composite layer is determined, the data is expanded evenly outward in all horizontal directions by a predetermined amount, .lambda., to produce data representing a preliminary expanded region. Any narrow regions are then merged together with the preliminary expanded region to produce data representing a final expanded region, which is used to produce a mask employed to produce an even width trench about the perimeter of the composite layer. The computer then generates the mask according to the results achieved and the isolation trenches are etched. The resulting isolation trenches prevent short-circuits from occurring between the various electrical devices on the semiconductor device.
摘要翻译：用于有效地产生有限的沟槽宽度隔离结构而不会产生对凹陷问题的敏感性以产生高质量IC的方法使用计算机产生表示沟槽隔离掩模的数据，所述沟槽隔离掩模能够用于围绕有源的周边刻蚀有限的沟槽宽度隔离结构区域层，多晶硅层和局部互连（LI）层。一旦使用计算机上的数据来定义各个层，并且配置为使得芯片空间最大化，则使用例如逻辑OR运算符来组合边界以产生表示整个复合层的数据。一旦确定了表示复合层的数据，则数据在所有水平方向上均匀地向外扩展预定量的λ，以产生表示初步扩展区域的数据。然后将任何窄区域与预扩展区域合并以产生表示最终扩展区域的数据，其用于产生用于围绕复合层的周边产生均匀宽度沟槽的掩模。然后，计算机根据实现的结果生成掩模，并且蚀刻隔离沟槽。所产生的隔离沟槽防止在半导体器件上的各种电器件之间发生短路。

14. 发明申请

US20050011621A1 Lignocellulose product 失效
标题翻译：木质纤维素产品
公开(公告)号：US20050011621A1
公开(公告)日：2005-01-20
申请号：US10494469
申请日：2002-10-31
申请人： Ulla Westermark , Olov Karlsson
发明人： Ulla Westermark , Olov Karlsson
IPC分类号： D21C9/00 , D21J3/00
CPC分类号： D21J3/00 , D21C9/004
摘要： The invention concerns a process for the production of activated fibres or particles having self-binding properties comprising the steps of treating fibres or particles of lignocellulose containing material by contacting them with an oxidant during a time sufficient for the formation of water soluble reaction products with binding properties and retaining at least a significant part of said water soluble reaction products with the treated fibres or particles. The invention further concerns activated fibres or particles obtainable by the process, a press moulded product and a process for the production thereof from activated fibres or particles.
摘要翻译：本发明涉及一种生产活性纤维或具有自结合性质的颗粒的方法，其包括以下步骤：通过在足以形成具有结合性的水溶性反应产物的时间内与氧化剂接触来处理含木素纤维素材料的纤维或颗粒所述水溶性反应产物与所处理的纤维或颗粒保留至少大部分所述水溶性反应产物。本发明还涉及通过该方法获得的活化纤维或颗粒，压制成型产品以及由活化的纤维或颗粒制备的方法。

15. 发明授权

US06239031B1 Stepper alignment mark structure for maintaining alignment integrity 有权
标题翻译：用于保持对准完整性的步进对准标记结构
公开(公告)号：US06239031B1
公开(公告)日：2001-05-29
申请号：US09487493
申请日：2000-01-19
申请人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyah , Effiong Ibok , Christopher F. Lyons
发明人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyah , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21302
CPC分类号： G03F9/7076 , G03F9/70 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： Accurate photolighographic processing is achieved employing a stepper global alignment structure enabling formation thereon of a substantially transparent layer having a substantially planar upper surface. Embodiments include a set of global alignment marks comprising spaced apart trenches, each trench segmented into a plurality of narrow trenches spaced apart by uprights and forming a dummy topographical area of narrow trenches surrounding the set of alignment marks. The segmented trenches and the dummy topographical area effectively provide a substantially uniform topography enabling deposition of a transparent layer without steps and effective local planarization. Since the upper surface of the transparent layer is substantially planar, layers of material deposited on the transparent layer during subsequent processing also have a substantially planar upper surface, thereby enabling transmission of the signal produced by the alignment marks to the stepper with minimal distortion.
摘要翻译：使用步进全局对准结构可实现准确的视差处理，该结构能够在其上形成具有基本平坦的上表面的基本透明的层。实施例包括一组包括间隔开的沟槽的全局对准标记，每个沟槽被分段成由立柱间隔开的多个窄沟槽，并形成围绕该组对准标记的窄沟槽的虚拟地形区域。分段沟槽和虚拟地形区域有效地提供基本均匀的形貌，使得能够沉积透明层而无需步骤和有效的局部平面化。由于透明层的上表面基本上是平面的，因此在随后的处理期间沉积在透明层上的材料层也具有基本平坦的上表面，从而能够以最小的变形将由对准标记产生的信号传输到步进机。

16. 发明授权

US06074927A Shallow trench isolation formation with trench wall spacer 失效
标题翻译：浅沟槽隔离形成与沟槽壁间隔
公开(公告)号：US06074927A
公开(公告)日：2000-06-13
申请号：US87662
申请日：1998-06-01
申请人： Nick Kepler , Basab Bandyopadhyay , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
发明人： Nick Kepler , Basab Bandyopadhyay , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232
摘要： A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges and protects the field oxide from gouging during post-gate processing, such as during the local interconnect etch, thereby allowing the formation of high-quality implanted junctions. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited in the trench on the oxide liner and on the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench is anisotropically etched, to remove the polish stop at the bottom of the trenches leaving a portion overlying the side surfaces and edges of the trench on the oxide liner. The trench is then filled with an insulating material, the insulating material is planarized, and the polish stop over the pad oxide layer is removed by anisotropic etching. Thus, the oxide liner is allowed to grow on the trench edges without the restraint of a polish stop, resulting in a thick, rounded oxide on the trench edges. The portion of the polish stop remaining in the trench and on the oxide liner at the trench edges serves as a protective spacer, protecting the field oxide from erosion during subsequent processing steps.
摘要翻译：形成浅沟槽隔离结构，其使得能够在沟槽边缘处生长高质量的栅极氧化物，并且保护场氧化物在后栅极处理（例如在局部互连蚀刻期间）中的气蚀，从而允许形成高质量植入路口。实施例包括直接在衬垫氧化物层上形成光致抗蚀剂掩模，衬垫氧化物层又形成在半导体衬底的主表面或半导体衬底上的外延层上。在掩模之后，蚀刻衬底以形成沟槽，在沟槽表面中生长氧化物衬垫，并且抛光停止层沉积在氧化物衬垫和衬垫氧化物层上的沟槽中。然后将抛光停止层掩蔽到沟槽边缘，并且沟槽中的抛光停止点被各向异性地蚀刻，以去除沟槽底部的抛光停止部，留下覆盖氧化物衬垫上的沟槽的侧表面和边缘的部分。然后用绝缘材料填充沟槽，使绝缘材料平坦化，并通过各向异性蚀刻去除衬垫氧化物层上的抛光剂停止。因此，允许氧化物衬垫在沟槽边缘上生长而不受抛光停止的限制，导致沟槽边缘上的厚的圆形氧化物。保留在沟槽中的抛光停止部分和在沟槽边缘处的氧化物衬垫上的部分用作保护间隔物，在随后的处理步骤期间保护场氧化物免受侵蚀。

17. 发明授权

US08635727B2 Variable-size bed 有权
标题翻译：可变大床
公开(公告)号：US08635727B2
公开(公告)日：2014-01-28
申请号：US12734324
申请日：2008-10-23
申请人： Johan Dahlin , Claes Lindh , Olov Karlsson , Håkan Karlsson
发明人： Johan Dahlin , Claes Lindh , Olov Karlsson , Håkan Karlsson
IPC分类号： A47C23/04
CPC分类号： B62D33/0612 , B60N2/24 , B60N2/34 , B60P3/39
摘要： The present invention relates to a variable-size bed (10) comprising a mattress core (16) and a base (14), which base is adapted to support at least a portion of the mattress core, wherein the mattress core and base have adjustable widths or lengths and each of the mattress core and base is changeable between an expanded state and a contracted state corresponding to an expanded state and a contracted state of the bed, respectively, and wherein the bed further comprises a cover means adapted to provide covering over the mattress core in both the expanded state and the contracted state of the bed. The present invention also relates to a vehicle comprising such a variable-size bed.
摘要翻译：本发明涉及一种包括床垫芯（16）和基座（14）的可变尺寸床（10），该基座适于支撑床垫芯的至少一部分，其中床垫芯和底座具有可调节宽度或长度，并且床垫芯和基座中的每一个分别在对应于床的膨胀状态和收缩状态的膨胀状态和收缩状态之间是可变的，并且其中床还包括适于提供覆盖物的覆盖装置床垫核心在扩张状态和床的合同状态。本发明还涉及一种包括这种可变尺寸床的车辆。

18. 发明申请

US20130115741A1 PROCESS TO REMOVE Ni AND Pt RESIDUES FOR NiPtSi APPLICATIONS USING AQUA REGIA WITH MICROWAVE ASSISTED HEATING 失效
标题翻译：使用微波炉辅助加热的NiPtSi应用去除Ni和Pt残留物的工艺
公开(公告)号：US20130115741A1
公开(公告)日：2013-05-09
申请号：US13292906
申请日：2011-11-09
申请人： Anh Duong , Olov Karlsson
发明人： Anh Duong , Olov Karlsson
IPC分类号： H01L21/336 , B08B7/00 , B08B3/08 , H01L21/28
CPC分类号： H01L21/02068 , C11D7/08 , C11D11/0047 , C11D11/007 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/66575 , H01L29/7848
摘要： The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process, comprising using an aqua regia cleaning solution (comprising a mixture of nitric acid and hydrochloric acid) with microwave assisted heating. Low boiling temperature of hydrochloric acid prevents heating the aqua regia solution to a high temperature, impeding the effectiveness of post silicidation nickel and platinum residue removal. Therefore, embodiments of the invention provide a microwave assisted heating of the substrate in an aqua regia solution, selectively heating platinum residues without significantly increasing the temperature of the aqua regia solution, rendering platinum residues to be more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.
摘要翻译：本发明公开了一种在镍铂硅化过程中从半导体衬底中清除残留物的方法，其中包括使用王水清洗溶液（包括硝酸和盐酸的混合物）与微波辅助加热。盐酸的低沸点温度可防止将王水溶液加热至高温，阻止后硅化镍和铂残渣去除的有效性。因此，本发明的实施方案提供了在王水溶液中微波辅助加热底物，选择性地加热铂残余物而不显着提高王水溶液的温度，使铂残留物更易溶于水溶液，从而将其从衬底的表面。

19. 发明授权

US06380047B1 Shallow trench isolation formation with two source/drain masks and simplified planarization mask 有权
标题翻译：浅沟槽隔离形成，具有两个源/漏屏蔽和简化的平面化掩模
公开(公告)号：US06380047B1
公开(公告)日：2002-04-30
申请号：US09634990
申请日：2000-08-08
申请人： Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
发明人： Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask with relatively few features having a relatively large geometry avoids the need to create and implement a complex and critical mask, thereby reducing manufacturing costs and increasing production throughput. Furthermore, because the large and small trenches are not polished at the same time, overpolishing is avoided, thereby improving planarity and, hence, the accuracy of subsequent photolithographic processing.
摘要翻译：使用简化的反向源极/漏极平面化掩模，在具有改善的平面度的半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。实施例包括形成大沟槽并用也覆盖衬底表面的绝缘材料再填充它们，掩蔽大沟槽上方的区域，蚀刻以基本上除去衬底表面上的所有绝缘材料，并抛光以平坦化绝缘材料沟渠然后形成围绕大沟槽的小沟槽和外围沟槽，用绝缘材料重新填充并平坦化。由于在小沟槽之前和分开形成大沟槽，所以可以在仅在大沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。使用具有相对较大几何特征的平面化掩模的使用避免了创建和实现复杂和关键掩模的需要，从而降低制造成本并提高生产量。此外，因为大的和小的沟槽不同时被抛光，所以避免了过度抛光，从而提高平面度，从而提高随后的光刻处理的精度。

20. 发明授权

US6124183A Shallow trench isolation formation with simplified reverse planarization mask 失效
标题翻译：浅沟槽隔离形成，具有简化的反向平面化掩模
公开(公告)号：US6124183A
公开(公告)日：2000-09-26
申请号：US992490
申请日：1997-12-18
申请人： Olov Karlsson , Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Larry Wang , Effiong Ibok
发明人： Olov Karlsson , Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Larry Wang , Effiong Ibok
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers a main surface of the substrate, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, furnace annealing to densify and strengthen the remaining insulating material, masking the insulating material above the large trenches, isotropically etching the insulating material, and polishing to planarize the insulating material. Since the insulating material is partially planarized and strengthened prior to etching, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. Because the features of the planarization mask are relatively few and have a relatively large geometry, the present invention avoids the need to create and implement a critical mask, enabling production costs to be reduced and manufacturing throughput to be increased.
摘要翻译：使用简化的反向源极/漏极平面化掩模在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。实施例包括形成沟槽并用绝缘材料再填充它们，该绝缘材料也覆盖衬底的主表面，抛光以除去绝缘材料的上部并平面化小沟槽上方的绝缘材料，炉退火致密化并加强其余部分绝缘材料，掩蔽大沟槽上方的绝缘材料，各向同性地蚀刻绝缘材料，并抛光以使绝缘材料平坦化。由于在蚀刻之前绝缘材料被部分平坦化和加强，因此可以在仅在大的沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。由于平面化掩模的特征相对较少并且具有相对较大的几何形状，因此本发明避免了创建和实施关键掩模的需要，从而能够降低生产成本并提高生产量。

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