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11. 发明授权

US06421574B1 Automatic defect classification system based variable sampling plan 有权
标题翻译：基于自动缺陷分类系统的可变抽样方案
公开(公告)号：US06421574B1
公开(公告)日：2002-07-16
申请号：US09404079
申请日：1999-09-23
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G06F1900
CPC分类号： H01L22/20
摘要： A method of manufacturing semiconductor devices in which scan data for a current layer of a wafer of a lot being manufactured is compared to previous scan data for previous lots that has been stored in a defect management system. The automatic defect classification system determines whether additional wafers need to be scanned in order to obtain accurate defect data for the production lot to determine whether the current lot should or should not be placed on hold.
摘要翻译：一种制造半导体器件的方法，其中将要制造的批次的晶片的当前层的扫描数据与已经存储在缺陷管理系统中的先前批次的先前扫描数据进行比较。自动缺陷分类系统确定是否需要扫描附加晶片，以获得生产批次的准确缺陷数据，以确定当前批次是否应该被搁置。

12. 发明授权

US06338001B1 In line yield prediction using ADC determined kill ratios die health statistics and die stacking 有权
标题翻译：在线产量预测使用ADC确定的死亡率死亡健康统计和死亡堆叠
公开(公告)号：US06338001B1
公开(公告)日：2002-01-08
申请号：US09255108
申请日：1999-02-22
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G06F1900
CPC分类号： H01L22/20
摘要： A method of manufacturing and inspecting semiconductor devices wherein defects on inspection wafers are tabulated in a stacked defect table wherein a defect table for each layer is generated per die number and a calculated cumulative die health statistic using an automatic defect classification system and a kill ratio for each defect. The cumulative die health statistic is carried over to the next defect table generated for the next layer.
摘要翻译：一种制造和检查半导体器件的方法，其中检查晶片上的缺陷被列在堆叠缺陷表中，其中使用自动缺陷分类系统生成每层的缺陷表，并且使用自动缺陷分类系统和杀死率每个缺陷。累积的模具健康状况统计量转移到为下一层生成的下一个缺陷表。

13. 发明授权

US06291332B1 Electroless plated semiconductor vias and channels 有权
标题翻译：无电镀半导体通孔和通道
公开(公告)号：US06291332B1
公开(公告)日：2001-09-18
申请号：US09416383
申请日：1999-10-12
申请人： Allen S. Yu , Paul J. Steffan
发明人： Allen S. Yu , Paul J. Steffan
IPC分类号： H01L214763
CPC分类号： H01L21/76874 , H01L21/288 , H01L21/76879
摘要： A method of manufacturing a semiconductor device is provided in which a semiconductor substrate with a dielectric layer has channel and via openings formed in the dielectric layer. A seed layer is formed over the dielectric layer and in the openings followed by a resist over the seed layer. The resist is then removed outside the openings. The seed layer outside the openings, which is not covered by the resist, is removed and the seed layer in the openings remains intact because of the resist in the openings. The resist inside the openings is removed and the seed layer inside the openings is electroless plated to fill the openings and form the channels and vias for interconnecting the semiconductor device.
摘要翻译：提供了一种制造半导体器件的方法，其中具有介电层的半导体衬底具有形成在电介质层中的沟道和通孔。种子层形成在电介质层之上，并且在开口中形成，随后是种子层上的抗蚀剂。然后将抗蚀剂从开口外部移除。由开口内的抗蚀剂除去未被抗蚀剂覆盖的开口外部的种子层，并且开口中的种子层保持完整。开口内的抗蚀剂被去除，并且开口内的种子层被无电镀以填充开口并形成用于互连半导体器件的通道和通路。

14. 发明授权

US06287922B1 Method for fabricating graded LDD transistor using controlled polysilicon gate profile 有权
标题翻译：使用受控多晶硅栅极型材制造分级LDD晶体管的方法
公开(公告)号：US06287922B1
公开(公告)日：2001-09-11
申请号：US09162426
申请日：1998-09-28
申请人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
发明人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
IPC分类号： H01L21336
CPC分类号： H01L29/66598 , H01L21/28114 , H01L21/823814 , H01L21/82385 , H01L29/665 , H01L29/66545 , H01L29/6659 , Y10S438/978
摘要： An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer, forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles.
摘要翻译：通过在半导体衬底上形成栅氧化层，制造具有逐渐掺杂分布和降低工艺复杂度的LDD结构的超大规模CMOS集成电路半导体器件; 在所述栅极氧化物层上形成多晶硅层，在所述多晶硅层上形成第一掩模层; 图案化和蚀刻第一掩模层以形成第一栅极掩模; 各向异性蚀刻所述多晶硅层以形成第一多晶硅栅极，其中所述第一多晶硅栅极具有倾斜轮廓的侧壁，以及用掺杂剂注入所述半导体衬底以穿透所述侧壁的部分以形成具有逐渐掺杂分布的一个或多个渐变浅结。

15. 发明授权

US06284553B1 Location dependent automatic defect classification 有权
标题翻译：位置依赖自动缺陷分类
公开(公告)号：US06284553B1
公开(公告)日：2001-09-04
申请号：US09251012
申请日：1999-02-16
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G01R3126
CPC分类号： H01L22/20
摘要： A method of manufacturing semiconductor devices wherein defects on each layer of a semiconductor wafer are determined to be killer or non-killer defects by correlating critical area information on a die with defect size and classification information. The killer/non-killer defect information is tabulated in a defect table from which statistical yield predictions can be made.
摘要翻译：一种制造半导体器件的方法，其中半导体晶片的每个层上的缺陷通过将具有缺陷尺寸和分类信息的裸片上的关键区域信息相关联来确定为杀伤性或非杀伤性缺陷。杀手/非杀手级缺陷信息列在缺陷表中，从中可以进行统计收益预测。

16. 发明授权

US06204133B1 Self-aligned extension junction for reduced gate channel 有权
标题翻译：自对准延伸结，用于减少栅极通道
公开(公告)号：US06204133B1
公开(公告)日：2001-03-20
申请号：US09586516
申请日：2000-06-02
申请人： Allen S. Yu , Paul J. Steffan
发明人： Allen S. Yu , Paul J. Steffan
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L21/2255 , H01L29/665
摘要： A method of manufacturing a semiconductor device having self-aligned extension junctions and a reduced gate channel length by etching an opening in a layer of phosphoro silicate glass that has been deposited on a substrate. The layer of phosphoro silicate glass serves as a self-aligned solid diffusion source to form LDD extensions. Spacers are formed on the walls of the opening in the phosphoro silicate glass and serve to reduce the length of the gate channel. A gate structure is formed by depositing a layer of gate oxide in the opening in the layer of phosphoro silicate glass and a layer of polysilicon is formed over the layer of gate oxide.
摘要翻译：一种制造具有自对准延伸接头的半导体器件的方法和通过蚀刻沉积在衬底上的磷硅玻璃层中的开口来减小栅极沟道长度的方法。磷硅玻璃层用作自对准固体扩散源以形成LDD延伸。垫片形成在磷硅玻璃中的开口的壁上，用于减小栅极通道的长度。通过在磷硅玻璃层中的开口中沉积栅极氧化物层而形成栅极结构，并且在栅极氧化物层上形成多晶硅层。

17. 发明授权

US06200823B1 Method for isolation of optical defect images 有权
标题翻译：隔离光学缺陷图像的方法
公开(公告)号：US06200823B1
公开(公告)日：2001-03-13
申请号：US09247241
申请日：1999-02-09
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G01R3126
CPC分类号： G09G3/006 , H01L22/12
摘要： A method of manufacturing semiconductor devices wherein defect images are isolated from reference images in an optical tool. Each layer of a semiconductor are inspected for defects and identified defect images are subtracted from reference images providing an operator of the optical tool a resultant image of the defects or a highlighted image of the defect.
摘要翻译：一种制造其中缺陷图像与光学工具中的参考图像隔离的半导体器件的方法。对每个半导体层进行缺陷检查，并从提供光学工具的操作者的参考图像中减去识别的缺陷图像，得到缺陷的结果图像或缺陷的突出图像。

18. 发明授权

US06191044B1 Method for forming graded LDD transistor using controlled polysilicon gate profile 失效
标题翻译：使用受控多晶硅栅极分布形成渐变LDD晶体管的方法
公开(公告)号：US06191044B1
公开(公告)日：2001-02-20
申请号：US09169275
申请日：1998-10-08
申请人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
发明人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
IPC分类号： H01L21302
CPC分类号： H01L29/6659 , H01L21/266 , H01L21/32137 , H01L29/36 , H01L29/42376 , H01L29/7833
摘要： An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having reduced polysilicon gate length, reduced parasitic capacitance and gradual doping profiles is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a polysilicon gate, wherein the polysilicon gate comprises sidewalls with re-entrant profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles. The gradual doping profiles reduce parasitic capacitance and minimize hot carrier injections. Portions of the polysilicon gates with re-entrant profiles are used as mask during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of the bottom portion of the polysilicon gates. Since the LDD structures are spaced away from the edges of the polysilicon gates, the lateral diffusion of the LDD structures into the channel due to rapid thermal annealing is reduced. This results in CMOS devices with reduced parasitic capacitance.
摘要翻译：通过在半导体衬底上形成栅极氧化层，制造具有降低的多晶硅栅极长度，降低的寄生电容和逐渐掺杂分布的LDD结构的超大规模CMOS集成电路半导体器件; 在所述栅极氧化物层上形成多晶硅层; 在所述多晶硅层上形成第一掩模层; 图案化和蚀刻第一掩模层以形成第一栅极掩模; 各向异性地蚀刻所述多晶硅层以形成多晶硅栅极，其中所述多晶硅栅极包括具有重入曲线的侧壁，以及用掺杂剂注入所述半导体衬底以穿透所述侧壁的部分以形成具有逐渐掺杂分布的一个或多个渐变浅结。逐渐的掺杂分布减少寄生电容并最大限度地减少热载流子注入。在LDD结构的离子注入期间，将具有重入分布的多晶硅栅极的部分用作掩模，以将所得到的LDD结构远离多晶硅栅极的底部的边缘。由于LDD结构与多晶硅栅极的边缘间隔开，所以LDD结构由于快速热退火而向沟道中的横向扩散减少。这导致具有降低的寄生电容的CMOS器件。

19. 发明授权

US6091138A Multi-chip packaging using bump technology 失效
标题翻译：多芯片封装采用凸点技术
公开(公告)号：US6091138A
公开(公告)日：2000-07-18
申请号：US32398
申请日：1998-02-27
申请人： Allen S. Yu , Paul J. Steffan , Thomas Charles Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas Charles Scholer
IPC分类号： H01L25/065 , H01L23/02
CPC分类号： H01L25/0652 , H01L2224/16145 , H01L2224/16225 , H01L2225/06562 , H01L2924/00014 , H01L2924/1515 , H01L2924/16195
摘要： A multichip integrated semiconductor device having a portion of a first chip bonded to electrical leads in a package using a flip chip technology such as solder bump technology and a second chip bonded to a second portion of the first chip using a flip chip technology such as solder bump technology.
摘要翻译：一种多芯片集成半导体器件，其具有使用诸如焊料凸块技术的倒装芯片技术将第一芯片的一部分结合到电引线的封装中，并且使用诸如焊料的倒装芯片技术将第二芯片接合到第一芯片的第二部分碰撞技术。

20. 发明授权

US06448606B1 Semiconductor with increased gate coupling coefficient 有权
标题翻译：半导体具有增加的栅极耦合系数
公开(公告)号：US06448606B1
公开(公告)日：2002-09-10
申请号：US09513261
申请日：2000-02-24
申请人： Allen S. Yu , Thomas C. Scholer , Paul J. Steffan
发明人： Allen S. Yu , Thomas C. Scholer , Paul J. Steffan
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A reduced device geometry semiconductor memory device is provided which has increased device efficiency because of an increased gate coupling coefficient. Shallow trench isolations are formed in a semiconductor substrate. The shallow trench isolations are selectively shaped in order to form a control gate dielectric layer later with a large width relative to the width between the floating gates.
摘要翻译：提供了一种缩小的器件几何形状半导体存储器件，其由于增加的栅极耦合系数而具有增加的器件效率。在半导体衬底中形成浅沟槽隔离。浅沟槽隔离件被选择成形以便稍后形成相对于浮动栅极之间宽度的大宽度的控制栅极电介质层。

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