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11. 发明授权

US6107827A FPGA CLE with two independent carry chains 有权
标题翻译： FPGA CLE具有两个独立的进位链
公开(公告)号：US6107827A
公开(公告)日：2000-08-22
申请号：US311782
申请日：1999-05-13
申请人： Steven P. Young , Bernard J. New , Nicolas John Camilleri , Trevor J. Bauer , Shekhar Bapat , Kamal Chaudhary , Sridhar Krishnamurthy
发明人： Steven P. Young , Bernard J. New , Nicolas John Camilleri , Trevor J. Bauer , Shekhar Bapat , Kamal Chaudhary , Sridhar Krishnamurthy
IPC分类号： H01L25/00 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17736 , H03K19/17796
摘要： The invention provides an FPGA comprising an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE). In one embodiment, the CLE is implemented in two similar portions called "slices". Each slice has a separate carry chain. In a CLE with four function generators, each carry chain incorporates the outputs of two function generators.
摘要翻译：本发明提供了一种包括相同瓦片阵列的FPGA。每个瓦片包括包括可配置逻辑元件（CLE）的逻辑块。在一个实施例中，CLE以称为“切片”的两个相似部分实现。每个切片都有一个单独的进位链。在具有四个功能发生器的CLE中，每个进位链包含两个功能发生器的输出。

12. 发明授权

US08293547B2 Hybrid integrated circuit device 有权
标题翻译：混合集成电路器件
公开(公告)号：US08293547B2
公开(公告)日：2012-10-23
申请号：US13038746
申请日：2011-03-02
申请人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
发明人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
IPC分类号： H01L21/00
CPC分类号： H03K19/177 , G06F17/5068 , H01L24/48 , H01L25/0657 , H01L2224/05553 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/19041 , H01L2924/37001 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.
摘要翻译：描述形成混合集成电路器件的方法的实施例。该方法的该实施例包括：使用第一光刻形成第一裸片，其中第一裸片位于衬底上; 以及使用第二光刻形成第二管芯，其中所述第二管芯位于所述第一管芯上。用于形成第一裸片的第一光刻是比用于形成第二裸片的第二光刻更大的光刻。第一个模具是IO模具。

13. 发明授权

US07480690B2 Arithmetic circuit with multiplexed addend inputs 有权
标题翻译：具有复用加法输入的算术电路
公开(公告)号：US07480690B2
公开(公告)日：2009-01-20
申请号：US11019854
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/48
CPC分类号： G06F7/509
摘要： Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.
摘要翻译：描述的是算术电路，逻辑上分为乘积发生器和加法器。逻辑上位于产品发生器和加法器之间的多路复用电路通过提供来自产品发生器的部分乘积到加法器的末端来支持常规功能。还可以控制复用电路以将多个外部添加的输入引导到加法器。附加加数输入可以包括从其他算术电路级联的输入和输出。

14. 发明授权

US07467177B2 Mathematical circuit with dynamic rounding 有权
标题翻译：具有动态四舍五入的数学电路
公开(公告)号：US07467177B2
公开(公告)日：2008-12-16
申请号：US11019853
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： G06F7/49963
摘要： Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M−1) and 2(M−1)−1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.
摘要翻译：描述了执行灵活舍入方案的数学电路。这些电路需要很少的额外资源，并且可以动态调整以改变舍入所涉及的位数。在一个实施例中，DSP电路存储从二进制数2（M-1）和2（M-1）-1组中选择的舍入常数，计算校正因子，并将舍入常数，校正因子和一个数据项以获得舍入的数据项。

15. 发明授权

US06201410B1 Wide logic gate implemented in an FPGA configurable logic element 有权
标题翻译：宽逻辑门在FPGA可配置逻辑元件中实现
公开(公告)号：US06201410B1
公开(公告)日：2001-03-13
申请号：US09374470
申请日：1999-08-13
申请人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
发明人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/1778
摘要： The invention allows the implementation of common wide logic functions using only two function generators of a field programmable gate array. One embodiment of the invention provides a structure for implementing a wide AND-gate in an FPGA configurable logic element (CLE) or portion thereof that includes no more than two function generators. First and second function generators are configured as AND-gates, the output signals (first and second AND signals) being combined in a 2-to-1 multiplexer controlled by the first AND signal, “0” selecting the first AND signal and “1” selecting the second AND signal. Therefore, a wide AND-gate is provided having a number of input signals equal to the total number of input signals for the two function generators. In another embodiment, a wide OR-gate is provided by configuring the function generators as OR-gates and controlling the multiplexer using the second OR signal.
摘要翻译：本发明允许仅使用现场可编程门阵列的两个函数发生器实现普通的宽逻辑功能。本发明的一个实施例提供了一种用于在FPGA可配置逻辑元件（CLE）或其部分中实现宽的与门的结构，其包括不超过两个功能发生器。第一和第二功能发生器被配置为与门，输出信号（第一和第二AND信号）被组合在由第一AND信号控制的2对1多路复用器中，选择第一AND信号为“0”和“1” “选择第二个AND信号。因此，提供了具有等于两个功能发生器的输入信号的总数的多个输入信号的宽AND门。在另一个实施例中，通过将功能发生器配置为OR门并使用第二OR信号来控制多路复用器来提供宽的或门。

16. 发明授权

US07567997B2 Applications of cascading DSP slices 有权
标题翻译：级联DSP片的应用
公开(公告)号：US07567997B2
公开(公告)日：2009-07-28
申请号：US11019518
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/48
CPC分类号： G06F7/5443
摘要： In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.
摘要翻译：在一个实施例中，公开了一种IC，其包括多个级联的数字信号处理片，其中每个片具有经由多路复用器耦合到加法器的乘法器，并且每个片与直接连接到相邻片; 以及用于通过例如opmode来配置多个数字信号处理片以执行一个或多个数学运算的装置。该IC允许实现一些基本的数学函数，例如加，减，乘和除。可以使用一个或多个DSP片段来实现许多其它应用，例如，累加，乘法累加（MACC），宽多路复用器，桶形移位器，计数器和折叠，抽取和内插FIR等等。

17. 发明授权

US06362648B1 Multiplexer for implementing logic functions in a programmable logic device 有权
标题翻译：用于在可编程逻辑器件中实现逻辑功能的多路复用器
公开(公告)号：US06362648B1
公开(公告)日：2002-03-26
申请号：US09712038
申请日：2000-11-13
申请人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
发明人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
IPC分类号： G06F738
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/1778
摘要： The invention allows the implementation of common wide logic functions using only two function generators of a field programmable gate array. One embodiment of the invention provides a structure for implementing a wide AND-gate in an FPGA configurable logic element (CLE) or portion thereof that includes no more than two function generators. First and second function generators are configured as AND-gates, the output signals (first and second AND signals) being combined in a 2-to-1 multiplexer controlled by the first AND signal, “0” selecting the first AND signal and “1” selecting the second AND signal. Therefore, a wide AND-gate is provided having a number of input signals equal to the total number of input signals for the two function generators. In another embodiment, a wide OR-gate is provided by configuring the function generators as OR-gates and controlling the multiplexer using the second OR signal.
摘要翻译：本发明允许仅使用现场可编程门阵列的两个函数发生器实现普通的宽逻辑功能。本发明的一个实施例提供了一种用于在FPGA可配置逻辑元件（CLE）或其部分中实现宽的与门的结构，其包括不超过两个功能发生器。第一和第二功能发生器被配置为与门，输出信号（第一和第二AND信号）被组合在由第一AND信号控制的2对1多路复用器中，选择第一AND信号为“0”和“1” “选择第二个AND信号。因此，提供了具有等于两个功能发生器的输入信号的总数的多个输入信号的宽AND门。在另一个实施例中，通过将功能发生器配置为OR门并使用第二OR信号来控制多路复用器来提供宽的或门。

18. 发明授权

US6072348A Programmable power reduction in a clock-distribution circuit 失效
标题翻译：时钟分配电路中的可编程功耗降低
公开(公告)号：US6072348A
公开(公告)日：2000-06-06
申请号：US890952
申请日：1997-07-09
申请人： Bernard J. New , Trevor J. Bauer , Steven P. Young
发明人： Bernard J. New , Trevor J. Bauer , Steven P. Young
IPC分类号： G06F1/08 , G06F1/32 , H03K1/04
CPC分类号： G06F1/32 , G06F1/08
摘要： A clock distribution circuit and method for programmable ICs whereby the incoming clock frequency is optionally divided by two and distributed at the new, lower frequency. Programmable dual-edge/single-edge flip-flops are provided that optionally operate at twice the frequency of the distributed clock, being responsive to both rising and falling edges of the distributed clock. When the clock divider is enabled and the flip-flops are programmed as dual-edge, the operating frequency is the same as that of the incoming clock; however, the frequency of the distributed clock is reduced by one-half. This reduction halves the frequency at which the clock distribution circuits operate, and consequently approximately halves the power dissipated by the clock distribution circuit, thereby providing a programmable power-saving mode.
摘要翻译：一种用于可编程IC的时钟分配电路和方法，其中输入时钟频率可选地被二分频并以新的较低频率分布。提供了可编程双边沿/单边沿触发器，可选地以分布式时钟频率的两倍工作，响应于分布式时钟的上升沿和下降沿。当时钟分频器使能并且触发器被编程为双边沿时，工作频率与输入时钟的工作频率相同; 然而，分布式时钟的频率减少了一半。这种减少将时钟分配电路工作的频率减半，从而将时钟分配电路消耗的功率大致减半，从而提供可编程省电模式。

19. 发明授权

US5963050A Configurable logic element with fast feedback paths 失效
标题翻译：具有快速反馈路径的可组态逻辑元件
公开(公告)号：US5963050A
公开(公告)日：1999-10-05
申请号：US823265
申请日：1997-03-24
申请人： Steven P. Young , Bernard J. New , Nicolas John Camilleri , Trevor J. Bauer , Shekhar Bapat , Kamal Chaudhary , Sridhar Krishnamurthy
发明人： Steven P. Young , Bernard J. New , Nicolas John Camilleri , Trevor J. Bauer , Shekhar Bapat , Kamal Chaudhary , Sridhar Krishnamurthy
IPC分类号： H01L25/00 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17736 , H03K19/17796
摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE) and an output multiplexer. Fast feedback paths are provided within the logic block to connect the CLE outputs to the CLE inputs, either directly or through an input multiplexer. The fast feedback paths bypass the output multiplexer and therefore provide faster feedback than can be obtained in most conventional FPGA logic blocks. In one embodiment, the fast feedback paths provide the ability for all function generators in one CLE to drive each other through fast feedback paths, regardless of how logic is mapped into the function generators of the CLE.
摘要翻译：本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。每个瓦片包括包括可配置逻辑元件（CLE）和输出多路复用器的逻辑块。在逻辑块内提供快速反馈路径，以将CLE输出直接或通过输入多路复用器连接到CLE输入。快速反馈路径绕过输出多路复用器，因此提供比在大多数常规FPGA逻辑块中可以获得的更快的反馈。在一个实施例中，快速反馈路径提供了一个CLE中的所有功能发生器通过快速反馈路径彼此驱动的能力，而不管逻辑如何映射到CLE的函数发生器中。

20. 发明授权

US09002915B1 Circuits for shifting bussed data 有权
标题翻译：用于转换总线数据的电路
公开(公告)号：US09002915B1
公开(公告)日：2015-04-07
申请号：US12417048
申请日：2009-04-02
申请人： Steven P. Young , Brian C. Gaide
发明人： Steven P. Young , Brian C. Gaide
IPC分类号： G06F7/00 , G06F15/00 , G06F5/01
CPC分类号： G06F5/015 , H03K19/17736
摘要： A circuit for shifting bussed data includes a first column of shift blocks, a compare block, and a second column of multiplexer blocks. The first column shifts the bussed data by a number of bits specified by first bits of a shift control input. The compare block determines the value of a second bit of the shift control input and creates an output reflecting that value. The second column has a control input coupled to the output of the compare block, shifts the data by one byte when the second bit of the shift control input has a first value, and does not shift the data when the second bit has a second value. The shift, compare, and multiplexer blocks can be substantially similar logic blocks programmable to perform any of these functions, can include N-bit data inputs and outputs, and can operate on the bussed data as an N-bit bus.
摘要翻译：用于移位总线数据的电路包括第一列移位块，比较块和第二列复用器块。第一列将总线数据移位由移位控制输入的第一位指定的位数。比较块确定移位控制输入的第二位的值，并创建反映该值的输出。第二列具有耦合到比较块的输出的控制输入，当移位控制输入的第二位具有第一值时将数据移位一个字节，并且当第二位具有第二值时不移位数据。移位，比较和多路复用器块可以是基本相似的可编程以执行这些功能的逻辑块，可以包括N位数据输入和输出，并且可以作为N位总线对总线数据进行操作。

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