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11. 发明授权

US07999304B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07999304B2
公开(公告)日：2011-08-16
申请号：US12026942
申请日：2008-02-06
申请人： Yoshio Ozawa , Akihito Yamamoto , Katsuaki Natori , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka
发明人： Yoshio Ozawa , Akihito Yamamoto , Katsuaki Natori , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka
IPC分类号： H01L29/76
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/512 , H01L29/513 , H01L29/66825 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate, and nonvolatile memory cells, each of the cells including a channel region having a channel length and a channel width, a tunnel insulating film, a floating gate electrode, a control gate electrode, an inter-electrode insulating film between the floating and control gate electrodes, and an electrode side-wall insulating film on side-wall surfaces of the floating and control gate electrodes, the electrode side-wall insulating film including first and second insulating films having first and second dielectric constants, the first dielectric constant being higher than the second dielectric constant, the second dielectric constant being higher than a dielectric constant of a silicon nitride film, the first insulating film being in a central region of a facing region between the floating and control gate electrodes, the second insulating region being in the both end regions of the facing region and protruding from the both end portions.
摘要翻译：半导体器件包括半导体衬底和非易失性存储单元，每个单元包括具有沟道长度和沟道宽度的沟道区，隧道绝缘膜，浮栅电极，控制栅电极，电极间绝缘在浮置控制栅电极和控制栅极电极的侧壁表面之间的电极侧壁绝缘膜，电极侧壁绝缘膜包括具有第一和第二介电常数的第一和第二绝缘膜，所述第一介电常数高于所述第二介电常数，所述第二介电常数高于氮化硅膜的介电常数，所述第一绝缘膜位于所述浮动栅极和控制栅电极之间的面对区域的中心区域中，第二绝缘区域位于面对区域的两端区域中并从两端口突出 ons。

12. 发明申请

US20110175048A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20110175048A1
公开(公告)日：2011-07-21
申请号：US13004287
申请日：2011-01-11
申请人： Katsuyuki SEKINE , Ryota FUJITSUKA , Yoshio OZAWA
发明人： Katsuyuki SEKINE , Ryota FUJITSUKA , Yoshio OZAWA
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/1273 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： According to one embodiment, a nonvolatile memory device includes first and second conductive layers, a resistance change layer, and a rectifying element. The first conductive layer has first and second major surfaces. The second conductive layer has third and fourth major surfaces, a side face, and a corner part. The third major surface faces the first major surface and includes a plane parallel to the first major face and is provided between the fourth and first major surfaces. The corner part is provided between the third major surface and the side face. The corner part has a curvature higher than that of the third major surface. The resistance change layer is provided between the first and second conductive layers. The rectifying element faces the second major surface of the first conductive layer. An area of the third major surface is smaller than that the second major surface.
摘要翻译：根据一个实施例，非易失性存储器件包括第一和第二导电层，电阻变化层和整流元件。第一导电层具有第一和第二主表面。第二导电层具有第三和第四主表面，侧面和拐角部分。第三主表面面向第一主表面并且包括平行于第一主面的平面，并且设置在第四主表面和第一主表面之间。角部设置在第三主表面和侧面之间。角部具有高于第三主表面的曲率。电阻变化层设置在第一和第二导电层之间。整流元件面向第一导电层的第二主表面。第三主表面的面积小于第二主表面的面积。

13. 发明授权

US07977728B2 Non-volatile NAND memory semiconductor integrated circuit 有权
标题翻译：非易失性NAND存储器半导体集成电路
公开(公告)号：US07977728B2
公开(公告)日：2011-07-12
申请号：US12715455
申请日：2010-03-02
申请人： Toshitake Yaegashi , Yoshio Ozawa
发明人： Toshitake Yaegashi , Yoshio Ozawa
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating film which is formed on the first insulating film and does not contain nitrogen as a main component, and a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in a partial region. The second insulating film is formed to fill the concave portions and a portion between the first and second gate electrodes has a multi-layered structure containing at least the first and second insulating films.
摘要翻译：半导体集成电路器件包括：第一，第二栅电极，第一，第二扩散层，电连接到第一扩散层的接触电极;第一绝缘膜，其在第一和第二栅电极之间具有凹入部分，并且不含氮作为主要成分，形成在第一绝缘膜上并且不含氮作为主要成分的第二绝缘膜和形成在第一扩散层上的第三绝缘膜，第一栅电极，第二扩散层和第二栅电极，第二绝缘膜设置在部分区域之间。形成第二绝缘膜以填充凹部，并且第一和第二栅电极之间的部分具有至少包含第一绝缘膜和第二绝缘膜的多层结构。

14. 发明申请

US20110143530A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110143530A1
公开(公告)日：2011-06-16
申请号：US13033017
申请日：2011-02-23
申请人： Atsuhiro SATO , Fumitaka Arai , Yoshio Ozawa , Takeshi Kamigaichi
发明人： Atsuhiro SATO , Fumitaka Arai , Yoshio Ozawa , Takeshi Kamigaichi
IPC分类号： H01L21/3205
CPC分类号： H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11546 , H01L29/7881
摘要： A semiconductor memory device according to the present invention includes: a first transistor formed on a semiconductor substrate 11, the first transistor including a first gate-insulating film 14a that is oxynitrided; and a second transistor including a second gate-insulating film 14b formed on the semiconductor substrate 11 and a barrier film 20 formed at least partially on the second gate-insulating film 14b, the second gate-insulating film having a lower nitrogen atom concentration than the first gate-insulating film.
摘要翻译：根据本发明的半导体存储器件包括：形成在半导体衬底11上的第一晶体管，所述第一晶体管包括被氮氧化的第一栅极绝缘膜14a; 以及第二晶体管，包括形成在半导体衬底11上的第二栅极绝缘膜14b和至少部分地形成在第二栅极绝缘膜14b上的阻挡膜20，第二栅极绝缘膜具有比第一栅极绝缘膜。

15. 发明申请

US20110069530A1 NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20110069530A1
公开(公告)日：2011-03-24
申请号：US12823467
申请日：2010-06-25
申请人： Katsuyuki SEKINE , Ryota Fujitsuka , Yoshio Ozawa
发明人： Katsuyuki SEKINE , Ryota Fujitsuka , Yoshio Ozawa
IPC分类号： G11C11/00 , H01L21/66
CPC分类号： G11C13/0069 , G11C11/005 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C2013/0083 , G11C2213/32 , G11C2213/34 , G11C2213/72 , H01L27/101
摘要： According to one embodiment, there is provided a method of manufacturing a nonvolatile memory device. In this method, a first voltage may be applied to a variable resistive element having a resistance value which is electrically rewritable in a high resistance and in a low resistance. In this method, a second voltage may be applied to the variable resistive element in a case where the resistance value of the variable resistive element to which the first voltage has been applied is greater than a resistance value of the low resistance and is not greater than a resistance value of the high resistance. Further, in this method, the applying of the second voltage to the variable resistive element may be repeated until the resistance value of the variable resistive element to which the second voltage has been applied falls within a range of the resistance value of the low resistance.
摘要翻译：根据一个实施例，提供了一种制造非易失性存储器件的方法。在该方法中，可以将第一电压施加到具有电阻可变的电阻值的高电阻和低电阻的可变电阻元件。在该方法中，在施加了第一电压的可变电阻元件的电阻值大于低电阻的电阻值的情况下，可以向可变电阻元件施加第二电压，并且不大于电阻值为高电阻。此外，在该方法中，可以重复向可变电阻元件施加第二电压，直到施加了第二电压的可变电阻元件的电阻值落在低电阻的电阻值的范围内。

16. 发明授权

US07888730B2 Nonvolatile semiconductor memory 有权
公开(公告)号：US07888730B2
公开(公告)日：2011-02-15
申请号：US11687758
申请日：2007-03-19
申请人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

17. 发明授权

US07863166B2 Method of manufacturing semiconductor storage device 有权
标题翻译：制造半导体存储装置的方法
公开(公告)号：US07863166B2
公开(公告)日：2011-01-04
申请号：US12646563
申请日：2009-12-23
申请人： Takashi Suzuki , Hirokazu Ishida , Ichiro Mizushima , Yoshio Ozawa , Fumiki Aiso , Katsuyuki Sekine , Takashi Nakao , Yoshihiko Saito
发明人： Takashi Suzuki , Hirokazu Ishida , Ichiro Mizushima , Yoshio Ozawa , Fumiki Aiso , Katsuyuki Sekine , Takashi Nakao , Yoshihiko Saito
IPC分类号： H01L21/20
CPC分类号： H01L27/115 , H01L21/76264 , H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/1203 , H01L29/66825
摘要： A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.
摘要翻译：一种制造半导体存储装置的方法包括在形成在硅衬底上的绝缘膜中的多个位置提供开口部分，然后在其中形成开口部分的绝缘膜上形成非晶硅膜，并且在开口部。然后，形成沟槽，将相邻的开口部之间的中点附近的非晶硅膜分割成一个开口部侧的一部分和另一个开口部侧的一部分。接着，对其中形成沟槽的非晶硅膜进行退火并进行固相结晶以形成具有用作晶种的开口部分的单晶，从而形成硅单晶层。然后，在硅单晶层上形成存储单元阵列。

18. 发明申请

US20100320522A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20100320522A1
公开(公告)日：2010-12-23
申请号：US12805620
申请日：2010-08-10
申请人： Yoshio Ozawa
发明人： Yoshio Ozawa
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , B30B11/004 , H01L29/42324 , H01L29/42336
摘要： A semiconductor device includes a tunnel insulation film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulation film, an inter-electrode insulation film formed on the floating gate electrode, a control gate electrode formed on the inter-electrode insulation film, a pair of oxide films which are formed between the tunnel insulation film and the floating gate electrode and are formed near lower end portions of a pair of side surfaces of the floating gate electrode, which are parallel in one of a channel width direction and a channel length direction, and a nitride film which is formed between the tunnel insulation film and the floating gate electrode and is formed between the pair of oxide films.
摘要翻译：半导体器件包括形成在半导体衬底上的隧道绝缘膜，形成在隧道绝缘膜上的浮栅电极，形成在浮栅上的电极间绝缘膜，形成在电极间绝缘膜上的控制栅电极形成在所述隧道绝缘膜和所述浮栅之间并且形成在所述浮栅电极的一对侧面的下端部附近的一对氧化膜，所述一对侧面在沟道宽度方向和沟道长度方向和形成在隧道绝缘膜和浮栅之间并形成在一对氧化膜之间的氮化物膜。

19. 发明申请

US20100314602A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20100314602A1
公开(公告)日：2010-12-16
申请号：US12728579
申请日：2010-03-22
申请人： Kensuke Takano , Yoshio Ozawa , Katsuyuki Sekine , Junichi Wada
发明人： Kensuke Takano , Yoshio Ozawa , Katsuyuki Sekine , Junichi Wada
IPC分类号： H01L45/00 , H01L21/28
CPC分类号： H01L45/08 , G11C11/5685 , G11C13/0007 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/1666
摘要： A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer
摘要翻译：非易失性存储器件包括：第一导电层; 第二导电层; 第一电阻变化层，设置在所述第一导电层和所述第二导电层之间，并且具有通过施加电场和通过电流中的至少一个而改变的电阻; 以及第一侧面层，设置在第一电阻变化层的侧面上，其氧浓度高于第一电阻变化层中的氧浓度

20. 发明申请

US20100237402A1 SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONALLY ARRANGED MEMORY CELLS, AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有三维方向记忆细胞的半导体存储器件及其制造方法
公开(公告)号：US20100237402A1
公开(公告)日：2010-09-23
申请号：US12726952
申请日：2010-03-18
申请人： Katsuyuki SEKINE , Kensuke TAKANO , Masaaki HIGUCHI , Tetsuya KAI , Yoshio OZAWA
发明人： Katsuyuki SEKINE , Kensuke TAKANO , Masaaki HIGUCHI , Tetsuya KAI , Yoshio OZAWA
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11578 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/42332 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.
摘要翻译：第一选择晶体管形成在半导体衬底上。存储单元晶体管堆叠在第一选择晶体管上并串联连接。在存储单元晶体管上形成第二选择晶体管。存储单元晶体管包括从第一选择晶体管朝向第二选择晶体管的直径增加的锥形半导体柱，形成在半导体柱的侧表面上的隧道电介质膜，形成在半导体柱的侧表面上的电荷存储层隧道电介质膜，并且其从第一选择晶体管侧朝向第二选择晶体管侧的电荷陷阱密度增加，形成在电荷存储层的侧表面上的块状电介质膜和形成在电荷存储层的侧表面上的导体膜该块介质膜并用作栅电极。

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