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11. 发明授权

US06833726B2 SOI-LDMOS device with integral voltage sense electrodes 有权
公开(公告)号：US06833726B2
公开(公告)日：2004-12-21
申请号：US10779093
申请日：2004-02-13
申请人： John Petruzzello , Benoit Dufort , Theodore Letavic
发明人： John Petruzzello , Benoit Dufort , Theodore Letavic
IPC分类号： G01R3126
CPC分类号： H01L29/404 , H01L27/1203 , H01L29/42368 , H01L29/7824 , H01L29/7826
摘要： The present invention provides a semiconductor device of the SOI-LDMOS type in which the field plate is divided into a plurality of electrically isolated sub-field plates. At least two of the divided sub-field plates are connected to external circuits for reading their respective output voltages. By connecting a first external circuit and a second external circuit having specific components, one is configured for determining an instantaneous output voltage and the other is configured for determining a change in output voltage as a function of time. Power is disconnected from the semiconductor device if either the instantaneous voltage or the derivative of voltage over time exceeds an established value.

12. 发明授权

US6127703A Lateral thin-film silicon-on-insulator (SOI) PMOS device having a drain extension region 有权
标题翻译：具有漏极延伸区域的横向薄膜绝缘体上硅（SOI）PMOS器件
公开(公告)号：US6127703A
公开(公告)日：2000-10-03
申请号：US387628
申请日：1999-08-31
申请人： Theodore Letavic , Mark Simpson
发明人： Theodore Letavic , Mark Simpson
IPC分类号： H01L29/06 , H01L29/786 , H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/78624 , H01L29/0615
摘要： A lateral thin-film Silicon-On-Insulator (SOI) PMOS device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral PMOS transistor device in an SOI layer on the buried insulating layer and having a source region of p-type conductivity formed in a body region of n-type conductivity. A lateral drift region of n-type conductivity is provided adjacent the body region, and a drain region of p-type conductivity is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region. In order to simply and economically implement the PMOS transistor device, the lateral drift region is provided with a linearly-graded charge profile over at least a major portion of its lateral extent and a surface-adjoining p-type conductivity drain extension region is provided in the drift region and extends from the drain region to adjacent to, but not in direct contact with, the source region.
摘要翻译：横向薄膜绝缘体上硅（SOI）PMOS器件包括半导体衬底，衬底上的掩埋绝缘层和掩埋绝缘层上的SOI层中的横向PMOS晶体管器件，并且具有p- 在n型导电体的体区形成的导电型。在身体区域附近设置有n型导电性的横向漂移区域，并且通过漂移区域与身体区域横向间隔设置有p型导电性的漏极区域。栅电极设置在主体区域的一部分上，其中在操作期间形成沟道区，并且在邻近身体区域的横向漂移区的一部分上延伸，栅电极与身体区域和漂移区域绝缘绝缘区域。为了简单且经济地实现PMOS晶体管器件，横向漂移区域在其横向范围的至少大部分上被提供有线性渐变的电荷分布，并且表面相邻的p型导电漏极延伸区域设置在漂移区域并且从漏极区域延伸到与源极区域相邻但不直接接触源极区域。

13. 发明授权

US5973341A Lateral thin-film silicon-on-insulator (SOI) JFET device 有权
标题翻译：横向薄膜绝缘体上硅（SOI）JFET器件
公开(公告)号：US5973341A
公开(公告)日：1999-10-26
申请号：US211149
申请日：1998-12-14
申请人： Theodore Letavic , Erik Peters , Rene Zingg
发明人： Theodore Letavic , Erik Peters , Rene Zingg
IPC分类号： H01L21/337 , H01L29/808 , H01L29/80 , H01L31/112
CPC分类号： H01L29/8086
摘要： A lateral thin-film Silicon-On-Insulator (SOI) JFET device includes a semiconductor substrate, a buried insulating on the substrate, and a JFET device in a thin semiconductor layer of a first conductivity type on the buried insulating layer. The device includes a source region of the first conductivity type, a control region of a second conductivity type which is laterally spaced apart from the source region and a lateral drift region of the first conductivity type adjacent to the control region. A drain region of the first conductivity type is provided laterally spaced apart from the control region in a first lateral direction by the lateral drift region, and at least one field plate electrode is provided over at least a major portion of the lateral drift region and is insulated from the drift region by an insulation region. The control region includes control region segments which are spaced apart in a second lateral direction perpendicular to the first lateral direction by portions of the thin semiconductor layer, thus providing a normally "on" JFET device.
摘要翻译：横向薄膜绝缘体上硅绝缘体（SOI）JFET器件包括半导体衬底，衬底上的埋入绝缘层，以及在掩埋绝缘层上的第一导电类型的薄半导体层中的JFET器件。该器件包括第一导电类型的源极区域，与源极区域横向间隔开的第二导电类型的控制区域和与控制区域相邻的第一导电类型的横向漂移区域。第一导电类型的漏极区域通过横向漂移区域在第一横向方向上与控制区域横向间隔开，并且至少一个场板电极设置在横向漂移区域的至少大部分上，并且是通过绝缘区域与漂移区域绝缘。控制区域包括通过薄半导体层的一部分在垂直于第一横向方向的第二横向方向间隔开的控制区段，从而提供正常的“上”JFET器件。

14. 发明授权

US07968938B2 High-voltage device structure 有权
标题翻译：高压器件结构
公开(公告)号：US07968938B2
公开(公告)日：2011-06-28
申请号：US11629766
申请日：2005-06-10
申请人： Theodore Letavic , John Petruzzello
发明人： Theodore Letavic , John Petruzzello
IPC分类号： H01L29/94
CPC分类号： H01L29/407
摘要： The present invention provides a vertical tapered dielectric high-voltage device (10) in which the device drift region is depicted by action of MOS field plates (30) formed in vertical trenches. The high-voltage device comprises: a substrate (32); a silicon mesa (20) formed on the substrate and having a stripe geometry, wherein the silicon mesa provides a drift region having a constant doping profile; a recessed gate (22) and source (SN) formed on the silicon mesa; a trench (26) adjacent each side of the silicon mesa; and a metal-dielectric field plate structure (12) formed in each trench; wherein each metal-dielectric field plate structure comprises a dielectric (28) and a metal field plate (30) formed over the dielectric, and wherein a thickness of the dielectric increases linearly through a depth of the trench to provide a constant longitudinal electric field.
摘要翻译：本发明提供一种垂直锥形介质高压装置（10），其中通过在垂直沟槽中形成的MOS场板（30）的作用来描绘器件漂移区。高电压装置包括：基板（32）; 形成在所述衬底上并具有条纹几何形状的硅台面（20），其中所述硅台面提供具有恒定掺杂分布的漂移区域; 形成在硅台面上的凹入栅极（22）和源极（SN）; 与硅台面的每一侧相邻的沟槽（26）; 和形成在每个沟槽中的金属 - 电介质场板结构（12）其中每个金属 - 电介质场板结构包括形成在所述电介质上的电介质（28）和金属场板（30），并且其中所述电介质的厚度通过所述沟槽的深度线性增加以提供恒定的纵向电场。

15. 发明申请

US20080308874A1 Complementary Asymmetric High Voltage Devices and Method of Fabrication 审中-公开
标题翻译：互补非对称高压器件及其制作方法
公开(公告)号：US20080308874A1
公开(公告)日：2008-12-18
申请号：US11910613
申请日：2006-03-30
申请人： Theodore Letavic , Herman Effing , Robert Cook
发明人： Theodore Letavic , Herman Effing , Robert Cook
IPC分类号： H01L29/00 , H01L21/8238
CPC分类号： H01L29/0878 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/42368 , H01L29/66681 , H01L29/7816 , H01L29/7835 , H01L29/7838
摘要： An asymmetric semiconductor device (10) and method of forming the same in which 25V devices can be fabricated in processes with gate oxide thicknesses designed for 2.75 or 5.5V maximum operation. The device includes: a shallow trench isolation (STI) region (12) that forms a dielectric between a drain region (18) and a gate region (20) of a unit cell to allow for high voltage operation; and an n-type well (14) and a p-type well (24) patterned within the unit cell.
摘要翻译：一种非对称半导体器件（10）及其形成方法，其中可以在最大操作为2.75或5.5V的栅极氧化物厚度的工艺中制造25V器件。该器件包括：浅沟槽隔离（STI）区域（12），其在单元电池的漏极区域（18）和栅极区域（20）之间形成电介质，以允许高电压操作; 以及在单元电池内图案化的n型阱（14）和p型阱（24）。

16. 发明授权

US07439585B2 Silicon-on-insulator device 有权
标题翻译：绝缘体上硅器件
公开(公告)号：US07439585B2
公开(公告)日：2008-10-21
申请号：US10560067
申请日：2004-06-08
申请人： Theodore Letavic , John Petruzzello
发明人： Theodore Letavic , John Petruzzello
IPC分类号： H01L23/62
CPC分类号： H01L29/7824 , H01L27/1203 , H01L29/0615 , H01L29/063 , H01L29/1095
摘要： A Silicon on Insulator (SOI) device is disclosed wherein an extension of P-type doping (303) is implanted between the buried oxide layer of the device and the SOI layer. The extension is of a size and shape to permit the source (309) to be biased at a voltage significantly less than the handler wafer (304) and drain, a condition under which prior art SOI devices may not properly operate.
摘要翻译：公开了一种绝缘体上硅（SOI）器件，其中P型掺杂（303）的扩展被注入在器件的掩埋氧化物层和SOI层之间。延伸部具有尺寸和形状，以允许源极（309）以比处理器晶片（304）显着更小的电压偏置和漏极，这是现有技术的SOI器件可能无法正常工作的状态。

17. 发明申请

US20080128743A1 High-Voltage Device Structure 有权
标题翻译：高压器件结构
公开(公告)号：US20080128743A1
公开(公告)日：2008-06-05
申请号：US11629766
申请日：2005-06-10
申请人： Theodore Letavic , John Petruzzello
发明人： Theodore Letavic , John Petruzzello
IPC分类号： H01L29/739 , H01L29/78 , H01L21/336 , H01L21/331
CPC分类号： H01L29/407
摘要： The present invention provides a vertical tapered dielectric high-voltage device (10) in which the device drift region is depicted by action of MOS field plates (30) formed in vertical trenches. The high-voltage device comprises: a substrate (32); a silicon mesa (20) formed on the substrate and having a stripe geometry, wherein the silicon mesa provides a drift region having a constant doping profile; a recessed gate (22) and source (SN) formed on the silicon mesa; a trench (26) adjacent each side of the silicon mesa; and a metal-dielectric field plate structure (12) formed in each trench; wherein each metal-dielectric field plate structure comprises a dielectric (28) and a metal field plate (30) formed over the dielectric, and wherein a thickness of the dielectric increases linearly through a depth of the trench to provide a constant longitudinal electric field.
摘要翻译：本发明提供一种垂直锥形介质高压装置（10），其中通过在垂直沟槽中形成的MOS场板（30）的作用来描绘器件漂移区。高电压装置包括：基板（32）; 形成在所述衬底上并具有条纹几何形状的硅台面（20），其中所述硅台面提供具有恒定掺杂分布的漂移区域; 形成在硅台面上的凹入栅极（22）和源极（SN）; 与硅台面的每一侧相邻的沟槽（26）; 和形成在每个沟槽中的金属 - 电介质场板结构（12）其中每个金属 - 电介质场板结构包括电介质（28）和形成在所述电介质上的金属场板（30），并且其中所述电介质的厚度通过所述沟槽的深度线性增加以提供恒定的纵向电场。

18. 发明授权

US06661059B1 Lateral insulated gate bipolar PMOS device 有权
标题翻译：侧面绝缘栅双极PMOS器件
公开(公告)号：US06661059B1
公开(公告)日：2003-12-09
申请号：US10261254
申请日：2002-09-30
申请人： Theodore Letavic , John Petruzzello , Benoit Dufort
发明人： Theodore Letavic , John Petruzzello , Benoit Dufort
IPC分类号： H01L2976
CPC分类号： H01L29/7394
摘要： A lateral insulated gate bipolar PMOS device includes a semiconductor substrate, a buried insulating layer and a lateral PMOS transistor device in an SOI layer on the buried insulating layer having a source region of p-type conductivity. A lateral drift region of n-type conductivity is provided adjacent the body region, and a drain region of the p-type conductivity is provided laterally spaced from the body region by the drift region. An n-type conductivity drain region is formed of a shallow n-type contact surface region inserted into a p-inversion buffer. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region.
摘要翻译：横向绝缘栅极双极性PMOS器件包括在具有p型导电性的源极区域的掩埋绝缘层上的SOI层中的半导体衬底，埋入绝缘层和横向PMOS晶体管器件。在身体区域附近提供n型导电性的横向漂移区域，并且通过漂移区域与身体区域横向间隔设置p型导电性的漏极区域。 n型导电性漏极区域由插入p反转缓冲器的浅n型接触表面区域形成。栅电极设置在主体区域的一部分上，其中在操作期间形成沟道区，并且在邻近身体区域的横向漂移区的一部分上延伸，栅电极与身体区域和漂移区域绝缘绝缘区域。

19. 发明授权

US06310378B1 High voltage thin film transistor with improved on-state characteristics and method for making same 有权
标题翻译：具有改善导通状态特性的高压薄膜晶体管及其制造方法
公开(公告)号：US06310378B1
公开(公告)日：2001-10-30
申请号：US09539911
申请日：2000-03-30
申请人： Theodore Letavic , Mark Simpson , Emil Arnold
发明人： Theodore Letavic , Mark Simpson , Emil Arnold
IPC分类号： H01L2701
CPC分类号： H01L29/66681 , H01L21/266 , H01L29/0653 , H01L29/0847 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/41725 , H01L29/41733 , H01L29/42368 , H01L29/66674 , H01L29/66772 , H01L29/7813 , H01L29/7824 , H01L29/78624
摘要： The present invention is directed to an SOI LDMOS device having improved current handling capability, particularly in the source-follower mode, while maintaining an improved breakdown voltage capability. The improvement in current handling capability is achieved in a first embodiment by introducing an offset region between the source and thin drift regions. The offset region achieves an offset between the onset of the linear doping profile and the thinning of the SOI layer that results in the thin drift region. In a second embodiment a further increase in the current handling capability of an SOI device is achieved by fabricating an oxide layer over the offset region, with the thickness of the oxide layer layer varying up to about half the thickness of the oxide layer fabricated over the thin drift region.
摘要翻译：本发明涉及具有改善的电流处理能力的SOI LDMOS器件，特别是在源极跟随器模式中，同时保持改进的击穿电压能力。在第一实施例中，通过在源极和薄漂移区域之间引入偏移区域来实现电流处理能力的改善。偏移区域实现线性掺杂分布的开始和导致薄漂移区域的SOI层的薄化之间的偏移。在第二实施例中，SOI器件的电流处理能力的进一步增加是通过在偏移区域上制造氧化物层来实现的，其中氧化物层层的厚度变化到在其上制造的氧化物层的厚度的大约一半薄漂移区域。

20. 发明授权

US6096663A Method of forming a laterally-varying charge profile in silicon carbide substrate 失效
标题翻译：在碳化硅衬底中形成横向变化的电荷分布的方法
公开(公告)号：US6096663A
公开(公告)日：2000-08-01
申请号：US119282
申请日：1998-07-20
申请人： Dev Alok , Nikhil Taskar , Theodore Letavic
发明人： Dev Alok , Nikhil Taskar , Theodore Letavic
IPC分类号： H01L21/266 , C04B28/02 , H01L21/04 , H01L21/265 , H01L21/316
CPC分类号： H01L21/0465 , C04B35/565
摘要： A method of forming a laterally-varying charge profile in a silicon carbide substrate includes the steps of forming a silicon nitride layer on a polysilicon layer formed on the silicon carbide substrate, and patterning the silicon nitride layer to provide a plurality of silicon nitrite layer segments which are spaced apart in the lateral direction and which are provided with openings therebetween which are of varying widths. The polysilicon layer is oxidized using the layer segments as an oxidation mask to form a silicon dioxide layer of varying thickness from the polysilicon layer and to form a polysilicon layer portion therebeneath of varying thickness. The silicon dioxide layer and silicon nitride layer segments are removed, and a dopant is ion implanted into the silicon carbide substrate using the polysilicon layer portion of varying thickness as an implantation mask to form a laterally-varying charge profile in the silicon carbide substrate. This method provides an effective and commercially-feasible technique for forming various high-power lateral semiconductor devices, including MOSFET, JFET, diode and IGBT structures, with excellent high-temperature and high-power operating characteristics.
摘要翻译：在碳化硅衬底中形成横向变化的电荷分布的方法包括以下步骤：在形成在碳化硅衬底上的多晶硅层上形成氮化硅层，以及对氮化硅层进行构图以提供多个亚硝酸硅层段它们在横向方向上间隔开，并且在其间设有不同宽度的开口。使用层段作为氧化掩模来氧化多晶硅层，以从多晶硅层形成具有不同厚度的二氧化硅层，并形成其厚度变化的多晶硅层部分。去除二氧化硅层和氮化硅层段，并且使用不同厚度的多晶硅层部分将掺杂剂离子注入到碳化硅衬底中作为注入掩模，以在碳化硅衬底中形成横向变化的电荷分布。该方法提供了一种有效和商业上可行的技术，用于形成包括MOSFET，JFET，二极管和IGBT结构的各种高功率横向半导体器件，具有优异的高温和高功率工作特性。

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