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11. 发明授权

US5469444A Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels 失效
标题翻译：具有写入验证控制器的电可擦除和可编程非易失性存储器系统，使用两个参考电平
公开(公告)号：US5469444A
公开(公告)日：1995-11-21
申请号：US341955
申请日：1994-11-16
申请人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
发明人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
IPC分类号： G11C11/56 , G11C16/34 , G11C29/50 , G01R31/28
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/3404 , G11C16/3413 , G11C16/3418 , G11C16/3431 , G11C16/3459 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/0403 , G11C2211/5621
摘要： An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.
摘要翻译： EEPROM包括存储单元晶体管的阵列，其被分成每个包括串联连接的单元晶体管的NAND单元单元的单元块。读出放大器连接到位线和比较器。数据锁存电路连接到比较器，用于锁存从数据输入缓冲器提供的写入数据。在所选择的块中选择用于编程的所需单元晶体管被一次编程之后，执行写验证操作。比较器将从编程单元晶体管之一读取的实际数据与写入数据进行比较，以验证其写入状态。写验证过程使用限定允许变化范围的下限和上限的第一和第二参考电压来检查所得到的阈值电压的变化。如果使用第一电压的比较结果表明，不规则写入的单元晶体管保持不足阈值电压，其不足以落在该范围内，对于相同的单元晶体管，写操作继续进行。如果在使用第二电压的情况下的比较结果表明剩余写入过多的单元晶体管，则该块至少部分地被“保护”。

12. 发明授权

US4996669A Electrically erasable programmable read-only memory with NAND memory cell structure 失效
标题翻译：具有NAND存储单元结构的电可擦除可编程只读存储器
公开(公告)号：US4996669A
公开(公告)日：1991-02-26
申请号：US489967
申请日：1990-03-07
申请人： Tetsuo Endoh , Riichiro Shirota , Masaki Momodomi , Tomoharu Tanaka , Fujio Masuoka , Shigeyoshi Watanabe
发明人： Tetsuo Endoh , Riichiro Shirota , Masaki Momodomi , Tomoharu Tanaka , Fujio Masuoka , Shigeyoshi Watanabe
IPC分类号： G11C16/04
CPC分类号： G11C16/0483
摘要： An electrically erasable programmable read-only memory with a NAND cell structure has parallel bit lines, and memory cells defining NAND cell blocks, each of which has a series-circuit of memory cell transistors. Each transistor has a floating gate and a control gate. Parallel word lines are connected to the control gates of the cell transistors. The first, second and third intermediate voltages are used in the data write mode: the first voltage is lower than the "H" level voltage and higher than the "L" level voltage; the second and third voltages are higher than the first voltage and lower than the "H" level voltage. Data is written into a selected memory cell transistor of a NAND cell block, by applying the "H" level voltage to a word line connected to the selected transistor, applying the second voltage to the remaining unselected word lines, applying a corresponding bit line associated with the selected transistor with one of the first and third voltages which is selected in accordance with a logic level of the data, and applying unselected bit lines with the third voltage, whereby carriers are moved by tunneling from or to the floating gate of the selected memory cell transistor.
摘要翻译：具有NAND单元结构的电可擦除可编程只读存储器具有并行位线，以及限定NAND单元块的存储器单元，每个存储单元具有存储单元晶体管的串联电路。每个晶体管都有一个浮动栅极和一个控制栅极。并行字线连接到单元晶体管的控制栅极。在数据写入模式下使用第一，第二和第三中间电压：第一电压低于“H”电平电压并高于“L”电平电压; 第二和第三电压高于第一电压并低于“H”电平电压。将数据写入NAND单元块的选定的存储单元晶体管中，通过将“H”电平电压施加到连接到所选晶体管的字线，将第二电压施加到剩余的未选字线，施加相应的位线其中所选择的晶体管具有根据数据的逻辑电平选择的第一和第三电压中的一个，以及施加具有第三电压的未选择的位线，由此通过隧道从所选择的浮动栅极或者所选择的浮动栅极存储单元晶体管。

13. 发明授权

US08969944B2 Semiconductor integrated circuit and method of producing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US08969944B2
公开(公告)日：2015-03-03
申请号：US13697905
申请日：2011-05-13
申请人： Tetsuo Endoh , Seo Moon-Sik
发明人： Tetsuo Endoh , Seo Moon-Sik
IPC分类号： H01L29/792
CPC分类号： H01L27/11556 , G11C16/0425 , G11C16/0433 , G11C16/0483 , H01L27/088 , H01L27/11524 , H01L27/11551 , H01L29/42328 , H01L29/66477 , H01L29/66825 , H01L29/7883 , H01L29/7889
摘要： Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell 1 in the semiconductor integrated circuit is provided with: a semiconductor pillar 2 that serves as a channel; a floating gate 5 that circumferentially covers the semiconductor pillar 2 via a tunnel insulation layer 6 on the outer circumference of the semiconductor pillar 2; and a control gate 4 that circumferentially covers the semiconductor pillar via an insulating layer 8 on the outer circumference of the semiconductor pillar 2, and that circumferentially covers the floating gate 5 via an insulating layer 7 on the outer circumference of the floating gate.
摘要翻译：提供了一种半导体集成电路，其使用在电池之间没有干扰的新颖的垂直MOS晶体管，其能够使短沟道效应最小化，不具有热电子注入，并且不需要形成浅结。还提供了一种制造半导体集成电路的方法。半导体集成电路中的存储单元1设置有：作为通道的半导体柱2; 通过半导体柱2的外周上的隧道绝缘层6周向地覆盖半导体柱2的浮动栅极5; 以及通过半导体柱2的外周上的绝缘层8周向地覆盖半导体柱的控制栅极4，并且经由浮动栅极的外周上的绝缘层7周向地覆盖浮置栅极5。

14. 发明申请

US20100130011A1 SEMICONDUCTOR DEVICE FABRICATION METHOD 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20100130011A1
公开(公告)日：2010-05-27
申请号：US12623556
申请日：2009-11-23
申请人： TETSUO ENDOH , Eiichi Nishimura
发明人： TETSUO ENDOH , Eiichi Nishimura
IPC分类号： H01L21/308 , H01L21/302
CPC分类号： H01L21/3086 , H01L21/3088 , H01L29/66181 , H01L29/66787 , H01L29/66795
摘要： According to a disclosed semiconductor device fabrication method according to one embodiment of the present invention, a layer having a line-and-space pattern extending in one direction is etched using another layer having a line-and-space pattern extending in another direction intersecting the one direction, thereby obtaining a mask having two-dimensionally arranged dots. An underlying layer is etched using the mask, thereby providing two-dimensionally arranged pillars.
摘要翻译：根据本发明的一个实施例公开的半导体器件制造方法，使用具有在与另一方向相交的另一个方向上延伸的线间距图案的另一层蚀刻具有沿一个方向延伸的线间距图案的层从而获得具有二维排列的点的掩模。使用掩模蚀刻下层，由此提供二维布置的柱。

15. 发明授权

US06188611B1 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06188611B1
公开(公告)日：2001-02-13
申请号：US09408441
申请日：1999-09-29
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

16. 发明授权

US5895949A Semiconductor device having inversion inducing gate 失效
标题翻译：具有反向感应门的半导体器件
公开(公告)号：US5895949A
公开(公告)日：1999-04-20
申请号：US879790
申请日：1997-06-20
申请人： Tetsuo Endoh
发明人： Tetsuo Endoh
IPC分类号： G11C16/04 , H01L27/115 , H01L29/423 , H01L29/76
CPC分类号： H01L27/115 , G11C16/0483 , H01L29/42324
摘要： A semiconductor device is characterized by comprising a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a plurality of cell transistors each having a control gate formed on the semiconductor substrate through the first insulating film, a second insulating film formed on upper and side surfaces of the control gate, and a conductive film formed on at least the side surface of the control gate through the second insulating film.
摘要翻译：半导体器件的特征在于包括半导体衬底，形成在半导体衬底上的第一绝缘膜，多个单元晶体管，每个单元晶体管具有通过第一绝缘膜形成在半导体衬底上的控制栅极，第二绝缘膜形成在上部和控制栅极的侧表面和通过第二绝缘膜形成在至少控制栅极的侧表面上的导电膜。

17. 发明授权

US5824583A Non-volatile semiconductor memory and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US5824583A
公开(公告)日：1998-10-20
申请号：US949819
申请日：1997-10-14
申请人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
发明人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11519 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.
摘要翻译：本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。浮动栅极部分地覆盖沟道区域。因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。多个存储单元串联连接以构成基本块。相邻的基本块由增强型MOS晶体管分开。在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

18. 发明授权

US5523980A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5523980A
公开(公告)日：1996-06-04
申请号：US364990
申请日：1994-12-28
申请人： Koji Sakui , Hiroshi Nakamura , Tomoharu Tanaka , Masaki Momodomi , Fujio Masuoka , Kazunori Ohuchi , Tetsuo Endoh
发明人： Koji Sakui , Hiroshi Nakamura , Tomoharu Tanaka , Masaki Momodomi , Fujio Masuoka , Kazunori Ohuchi , Tetsuo Endoh
IPC分类号： G11C16/06 , G11C8/12 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/34 , H01L29/78 , G11C8/00
CPC分类号： G11C8/12 , G11C16/0483
摘要： A NAND-cell type EEPROM having a plurality of bit lines, a plurality of control gate lines intersecting with the bit lines, and a plurality of memory cells driven by applying a potential to the control gate lines for selectively storing data, supplying data to the bit lines and receiving data therefrom. The memory cells form a plurality of cell units. The memory cells constituting each cell unit are connected in series to one bit line by a common selecting gate transistor. A plurality of data latch circuits are provided on the bit lines, respectively, for storing data to be written into the memory cells selected by the control gate lines. Further, a plurality of selecting gate drivers are provided to correspond to the cell units, respectively, for driving the control gate lines. A row decoder decodes row addresses for driving the selecting gate drivers and the control gate lines. A plurality of block-address latch circuits are provided to correspond to the selecting gate drivers, respectively, for temporarily storing signals derived from a row address by the row decoder, thereby to select at least two of the selecting gate drivers at the same time in order to write data.
摘要翻译：具有多个位线的NAND单元型EEPROM，与位线相交的多个控制栅极线，以及通过向控制栅极线施加电位而驱动的多个存储单元，用于选择性地存储数据，向位线和从其接收数据。存储单元形成多个单元单元。构成每个单元单元的存储单元通过公共选择栅极晶体管串联连接到一个位线。分别在位线上提供多个数据锁存电路，用于存储要写入由控制栅极线选择的存储单元的数据。此外，分别提供多个选择栅极驱动器以对应于用于驱动控制栅极线的单元单元。行解码器解码用于驱动选择栅极驱动器和控制栅极线的行地址。提供多个块地址锁存电路以分别对应于选择栅极驱动器，用于临时存储由行解码器从行地址导出的信号，从而同时选择至少两个选择栅极驱动器命令写数据。

19. 发明授权

US5355332A Electrically erasable programmable read-only memory with an array of one-transistor memory cells 失效
标题翻译：具有单晶体管存储单元阵列的电可擦除可编程只读存储器
公开(公告)号：US5355332A
公开(公告)日：1994-10-11
申请号：US780933
申请日：1991-10-23
申请人： Tetsuo Endoh , Riichiro Shirota
发明人： Tetsuo Endoh , Riichiro Shirota
IPC分类号： G11C16/04 , G11C16/16 , H01L27/115 , G11C7/00 , G11C11/40 , H01L27/10
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/16
摘要： A floating gate tunneling metal oxide semiconductor transistor is formed on a semiconductive substrate as a cell of electrically erasable programmable read-only memory. The transistor includes a source and a drain spaced apart to define a channel region therebetween in the substrate. An insulated floating gate at least partially overlies the channel region and is capacitively coupled with the substrate. A control gate is insulatively disposed above the conductive layer and spans the channel region. The withstanding voltage of the drain is specifically set to range from a first voltage adapted to be applied to the drain during a read operation to a second voltage applied thereto for forcing the conductive layer to discharge.
摘要翻译：在半导体衬底上形成浮栅隧穿金属氧化物半导体晶体管作为电可擦除可编程只读存储器的单元。晶体管包括间隔开的源极和漏极，以在衬底中限定其间的沟道区域。绝缘浮栅至少部分地覆盖在沟道区上并与衬底电容耦合。控制栅极绝缘地设置在导电层之上并跨越沟道区。漏极的耐受电压具体设定为在读取操作期间适用于施加到漏极的第一电压到施加于漏极的第二电压以强制导电层放电的范围。

20. 发明授权

US5323039A Non-volatile semiconductor memory and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US5323039A
公开(公告)日：1994-06-21
申请号：US499342
申请日：1990-06-21
申请人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
发明人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/68
CPC分类号： H01L27/11519 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.
摘要翻译： PCT No.PCT / JP89 / 00942 Sec。 371 1990年6月21日第 102（e）日期1990年6月21日PCT提交1989年9月14日PCT公布。公开号WO90 / 04855 日期为1990年5月3日。本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。浮动栅极部分地覆盖沟道区域。因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。多个存储单元串联连接以构成基本块。相邻的基本块由增强型MOS晶体管分开。在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

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