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11. 发明授权

US06175417B1 Method and apparatus for detecting defects in the manufacture of an electronic device 有权
标题翻译：用于检测电子设备制造中的缺陷的方法和装置
公开(公告)号：US06175417B1
公开(公告)日：2001-01-16
申请号：US09532869
申请日：2000-03-22
申请人： Douglas Do , Ted Taylor
发明人： Douglas Do , Ted Taylor
IPC分类号： G01B908
CPC分类号： G01N21/95684 , Y10S977/773
摘要： The invention provides a unique method and apparatus for detecting defects in an electronic device. In one preferred embodiment, the electronic device is a semiconductor integrated circuit (IC), particularly one of a plurality of IC dies fabricated on a wafer of silicon or other semiconductor material. The defect detection operation is effectuated by a unique combination of critical dimension measurement and pattern defect inspection techniques. During the initial scan of the surface of the wafer, in an attempt to locate the appropriate area for a critical dimension (CD) feature or element that is to be measured, a “best fit” comparison is made between a reference image and scanned images. The critical dimension measurements are conducted on a “best fit” image. In addition, a “worst fit” comparison is made between the reference and scanned images. A “worst fit” determination represents pattern distortions or defects in the ICs under evaluation.
摘要翻译：本发明提供了一种用于检测电子设备中的缺陷的独特方法和装置。在一个优选实施例中，电子器件是半导体集成电路（IC），特别是在硅或其他半导体材料的晶片上制造的多个IC管芯中的一个。缺陷检测操作通过关键尺寸测量和图案缺陷检测技术的独特组合来实现。在晶片表面的初始扫描期间，为了定位要测量的关键尺寸（CD）特征或元件的适当区域，在参考图像和扫描图像之间进行“最佳拟合”比较。关键尺寸测量在“最佳拟合”图像上进行。此外，在参考和扫描图像之间进行“最差拟合”比较。 “最差拟合”确定表示评估中的IC中的模式失真或缺陷。

12. 发明授权

US6054173A Copper electroless deposition on a titanium-containing surface 失效
标题翻译：在含钛表面上的铜无电沉积
公开(公告)号：US6054173A
公开(公告)日：2000-04-25
申请号：US916219
申请日：1997-08-22
申请人： Karl Robinson , Ted Taylor
发明人： Karl Robinson , Ted Taylor
IPC分类号： C23C18/18 , C23C18/40 , H01L21/288 , H01L21/3205 , H01L21/768 , H01L23/52 , B05D5/12
CPC分类号： H01L21/76838 , H01L21/288 , H01L21/76879 , H01L21/76885 , Y10S438/903 , Y10S438/945 , Y10S438/976
摘要： A method for depositing copper on a titanium-containing surface of a substrate is provided. The method includes forming a patterned catalyst material on the substrate, such that the titanium-containing surface is exposed in selected regions. The catalyst material has an oxidation half-reaction potential having a magnitude that is greater than a magnitude of a reduction half-reaction potential of titanium dioxide. Copper is then deposited from an electroless solution onto the exposed regions of the titanium-containing surface.
摘要翻译：提供了一种在基板的含钛表面上沉积铜的方法。该方法包括在衬底上形成图案化的催化剂材料，使得含钛表面在选定的区域中暴露。催化剂材料具有氧化半反应势，其量值大于二氧化钛的还原半反应电位的量级。然后将铜从无电溶液沉积到含钛表面的暴露区域上。

13. 发明申请

US20110316091A1 Semiconductor Devices, Assemblies And Constructions 有权
标题翻译：半导体器件，组件和结构
公开(公告)号：US20110316091A1
公开(公告)日：2011-12-29
申请号：US13224804
申请日：2011-09-02
申请人： Ted Taylor , Xiawan Yang
发明人： Ted Taylor , Xiawan Yang
IPC分类号： H01L27/088
CPC分类号： H01L21/76283
摘要： Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
摘要翻译：本文公开的实施例包括其中一对开口形成为半导体材料的方法，其中开口通过半导体材料的部分彼此间隔开。衬套沿着开口的侧壁形成，然后半导体材料从开口的底部被各向同性地蚀刻以合并开口，从而完全地切割半导体材料段。本文公开的实施例可以用于形成SOI结构，并且在形成具有完全围绕通道区域的晶体管栅极的场效应晶体管中。本文公开的实施例还包括具有围绕通道区域的晶体管栅极的半导体结构以及其中绝缘材料将上半导体材料与下半导体材料完全分离的结构。

14. 外观设计

USD383861S Bicycle light 失效
公开(公告)号：USD383861S
公开(公告)日：1997-09-16
申请号：US59947
申请日：1996-09-18
申请人： Jamie Taylor , Ted Taylor , Laurie Taylor
设计人： Jamie Taylor , Ted Taylor , Laurie Taylor

15. 发明授权

US06452677B1 Method and apparatus for detecting defects in the manufacture of an electronic device 失效
标题翻译：用于检测电子设备制造中的缺陷的方法和装置
公开(公告)号：US06452677B1
公开(公告)日：2002-09-17
申请号：US09023925
申请日：1998-02-13
申请人： Douglas Do , Ted Taylor
发明人： Douglas Do , Ted Taylor
IPC分类号： G01B1100
CPC分类号： G01N21/95684 , Y10S977/773
摘要： The invention provides a unique method and apparatus for detecting defects in an electronic device. In one preferred embodiment, the electronic device is a semiconductor integrated circuit (IC), particularly one of a plurality of IC dies fabricated on a wafer of silicon or other semiconductor material. The defect detection operation is effectuated by a unique combination of critical dimension measurement and pattern defect inspection techniques. During the initial scan of the surface of the wafer, in an attempt to locate the appropriate area for a critical dimension (CD) feature or element that is to be measured, a “best fit” comparison is made between a reference image and scanned images. The critical dimension measurements are conducted on a “best fit” image. In addition, a “worst fit” comparison is made between the reference and scanned images. A “worst fit” determination represents pattern distortions or defects in the ICs under evaluation.
摘要翻译：本发明提供了一种用于检测电子设备中的缺陷的独特方法和装置。在一个优选实施例中，电子器件是半导体集成电路（IC），特别是在硅或其他半导体材料的晶片上制造的多个IC管芯中的一个。缺陷检测操作通过关键尺寸测量和图案缺陷检测技术的独特组合来实现。在晶片表面的初始扫描期间，为了定位要测量的关键尺寸（CD）特征或元件的适当区域，在参考图像和扫描图像之间进行“最佳拟合”比较。关键尺寸测量在“最佳拟合”图像上进行。此外，在参考和扫描图像之间进行“最差拟合”比较。 “最差拟合”确定表示评估中的IC中的模式失真或缺陷。

16. 发明授权

US6054172A Copper electroless deposition on a titanium-containing surface 有权
公开(公告)号：US6054172A
公开(公告)日：2000-04-25
申请号：US257854
申请日：1999-02-25
申请人： Karl Robinson , Ted Taylor
发明人： Karl Robinson , Ted Taylor
IPC分类号： C23C18/18 , C23C18/40 , H01L21/288 , H01L21/3205 , H01L21/768 , H01L23/52 , B05D5/12
CPC分类号： H01L21/76838 , H01L21/288 , H01L21/76879 , H01L21/76885 , Y10S438/903 , Y10S438/945 , Y10S438/976
摘要： A method for depositing copper on a titanium-containing surface of a substrate is provided. The method includes forming a patterned catalyst material on the substrate, such that the titanium-containing surface is exposed in selected regions. The catalyst material has an oxidation half-reaction potential having a magnitude that is greater than a magnitude of a reduction half-reaction potential of titanium dioxide. Copper is then deposited from an electroless solution onto the exposed regions of the titanium-containing surface.

17. 发明授权

US08614151B2 Method of etching a high aspect ratio contact 有权
标题翻译：蚀刻高纵横比接触的方法
公开(公告)号：US08614151B2
公开(公告)日：2013-12-24
申请号：US11969443
申请日：2008-01-04
申请人： Russell A. Benson , Ted Taylor , Mark Kiehlbauch
发明人： Russell A. Benson , Ted Taylor , Mark Kiehlbauch
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： C09K13/00 , H01L21/31116
摘要： Methods and an etch gas composition for etching a contact opening in a dielectric layer are provided. Embodiments of the method use a plasma generated from an etch gas composed of C4F8 and/or C4F6, an oxygen source, and a carrier gas in combination with tetrafluoroethane (C2F4) or a halofluorocarbon analogue of C2F4.
摘要翻译：提供了用于蚀刻介电层中的接触开口的蚀刻气体组合物。该方法的实施例使用由C4F8和/或C4F6，氧源和与四氟乙烷（C2F4）或C2F4的卤代烃类似物组合的载气组成的蚀刻气体产生的等离子体。

18. 发明授权

US08044479B2 Transistors, semiconductor devices, assemblies and constructions 有权
标题翻译：晶体管，半导体器件，组件和结构
公开(公告)号：US08044479B2
公开(公告)日：2011-10-25
申请号：US12424392
申请日：2009-04-15
申请人： Ted Taylor , Xiawan Yang
发明人： Ted Taylor , Xiawan Yang
IPC分类号： H01L21/70 , H01L27/146
CPC分类号： H01L21/76283
摘要： Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
摘要翻译：本文公开的实施例包括其中一对开口形成为半导体材料的方法，其中开口通过半导体材料的部分彼此间隔开。衬套沿着开口的侧壁形成，然后半导体材料从开口的底部被各向同性地蚀刻以合并开口，从而完全地切割半导体材料段。本文公开的实施例可以用于形成SOI结构，并且在形成具有完全围绕通道区域的晶体管栅极的场效应晶体管中。本文公开的实施例还包括具有围绕通道区域的晶体管栅极的半导体结构以及其中绝缘材料将上半导体材料与下半导体材料完全分离的结构。

19. 发明申请

US20090176375A1 Method of Etching a High Aspect Ratio Contact 有权
标题翻译：蚀刻高宽比接触的方法
公开(公告)号：US20090176375A1
公开(公告)日：2009-07-09
申请号：US11969443
申请日：2008-01-04
申请人： Russell A. Benson , Ted Taylor , Mark Kiehlbauch
发明人： Russell A. Benson , Ted Taylor , Mark Kiehlbauch
IPC分类号： H01L21/3065 , C09K13/00
CPC分类号： C09K13/00 , H01L21/31116
摘要： Methods and an etch gas composition for etching a contact opening in a dielectric layer are provided. Embodiments of the method use a plasma generated from an etch gas composed of C4F8 and/or C4F6, an oxygen source, and a carrier gas in combination with tetrafluoroethane (C2F4) or a halofluorocarbon analogue of C2F4.
摘要翻译：提供了用于蚀刻介电层中的接触开口的蚀刻气体组合物。该方法的实施例使用由C4F8和/或C4F6，氧源和与四氟乙烷（C2F4）或C2F4的卤代烃类似物组合的载气组成的蚀刻气体产生的等离子体。

20. 发明申请

US20080048298A1 Semiconductor devices, assemblies and constructions, and methods of forming semiconductor devices, assemblies and constructions 有权
标题翻译：半导体器件，组件和结构，以及形成半导体器件，组件和结构的方法
公开(公告)号：US20080048298A1
公开(公告)日：2008-02-28
申请号：US11511596
申请日：2006-08-28
申请人： Ted Taylor , Xiawan Yang
发明人： Ted Taylor , Xiawan Yang
IPC分类号： H01L29/06 , H01L23/58
CPC分类号： H01L21/76283
摘要： Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
摘要翻译：本文公开的实施例包括其中一对开口形成为半导体材料的方法，其中开口通过半导体材料的部分彼此间隔开。衬套沿着开口的侧壁形成，然后半导体材料从开口的底部被各向同性地蚀刻以合并开口，从而完全地切割半导体材料段。本文公开的实施例可以用于形成SOI结构，并且在形成具有完全围绕通道区域的晶体管栅极的场效应晶体管中。本文公开的实施例还包括具有围绕通道区域的晶体管栅极的半导体结构以及其中绝缘材料将上半导体材料与下半导体材料完全分离的结构。

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