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11. 发明授权

US06544852B1 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06544852B1
公开(公告)日：2003-04-08
申请号：US08093983
申请日：1993-07-19
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L29/41783
摘要： In a method for forming a self-aligned contact in a MOS-type semiconductor device, a gate electrode film is deposited on a semiconductor substrate and an insulating film is deposited on the gate electrode film. The gate electrode film and the insulating film are then patterned such that the portion of the device where the two films are located is higher than any other regions of the device. A side wall insulating film is formed on the side wall of the gate electrode and the insulating film. Source and drain regions are formed in the face of the substrate using the patterned gate electrode film as a mask. A conductor film is then deposited on the exposed surface of the semiconductor substrate, the first insulating film and the side wall insulating film. A flattening film is then deposited to flatten the surface of the semiconductor, and a region of the flattened film and the conductor film which is above the gate electrode film is etched, using a photoresist film as a mask. As a result, the thickness of the photoresist film used as a mask in etching the conductor film is thinnest at the portion above which are located the insulating film and the gate electrode. Consequently, an open space in the photoresist film can be made smaller than the width of the gate electrode, so as to prevent accidental etching of the source and drain regions.
摘要翻译：在用于在MOS型半导体器件中形成自对准接触的方法中，在半导体衬底上沉积栅电极膜，并且在栅电极膜上沉积绝缘膜。然后将栅电极膜和绝缘膜图案化，使得两个膜所在的器件的部分高于器件的任何其它区域。在栅电极和绝缘膜的侧壁上形成侧壁绝缘膜。使用图案化的栅电极膜作为掩模，在衬底的表面形成源区和漏区。然后在半导体衬底，第一绝缘膜和侧壁绝缘膜的暴露表面上沉积导体膜。然后沉积扁平膜以使半导体的表面平坦化，并且使用光致抗蚀剂膜作为掩模来蚀刻平坦化膜和位于栅电极膜上方的导体膜的区域。结果，在蚀刻导体膜时用作掩模的光致抗蚀剂膜的厚度在其上方位于绝缘膜和栅电极的部分是最薄的。因此，可以使光致抗蚀剂膜中的开放空间小于栅电极的宽度，以防止意外蚀刻源区和漏区。

12. 发明授权

US5352626A Method for making a semiconductor device having an isolated layer region on the side wall of a groove 失效
标题翻译：制造在槽的侧壁上具有隔离层区域的半导体器件的方法
公开(公告)号：US5352626A
公开(公告)日：1994-10-04
申请号：US153906
申请日：1993-11-17
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , Y10S148/117
摘要： Steps or grooves are formed in a surface of a semiconductor substrate of a semiconductor device having a plurality of semiconductor elements, and an isolation Layer is formed on regions that include the steps or side walls of the grooves.
摘要翻译：在具有多个半导体元件的半导体器件的半导体衬底的表面中形成台阶或凹槽，并且在包括沟槽的台阶或侧壁的区域上形成隔离层。

13. 发明授权

US5293061A Semiconductor device having an isolation layer region on the side wall of a groove 失效
标题翻译：在槽的侧壁上具有隔离层区域的半导体装置
公开(公告)号：US5293061A
公开(公告)日：1994-03-08
申请号：US978461
申请日：1992-11-19
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L21/762 , H01L29/06 , H01L29/00
CPC分类号： H01L21/76202 , Y10S148/117
摘要： Steps or grooves are formed in a surface of a semiconductor substrate of a semiconductor device having a plurality of semiconductor elements, and an isolation layer is formed on regions that include the steps or side walls of the grooves.
摘要翻译：在具有多个半导体元件的半导体器件的半导体衬底的表面上形成台阶或凹槽，并且在包括沟槽的台阶或侧壁的区域上形成隔离层。

14. 发明授权

US5149669A Method of forming an isolation region in a semiconductor device 失效
标题翻译：在半导体器件中形成隔离区域的方法
公开(公告)号：US5149669A
公开(公告)日：1992-09-22
申请号：US164431
申请日：1988-03-04
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L21/32 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76205
摘要： An isolation method which enables bird's beaks to be reduced and which also permits a reduction in the number of defects is disclosed. A masking layer which masks against field oxidation comprises a polycrystalline silicon film covered with silicon nitride films. The surface of the semiconductor substrate which is not masked by the masking layer is subjected to an oxidation treatment to form an element isolation region.
摘要翻译：公开了一种能够减少鸟嘴并且还允许减少缺陷数量的隔离方法。掩蔽场氧化的掩模层包括覆盖有氮化硅膜的多晶硅膜。对未被掩模层掩蔽的半导体衬底的表面进行氧化处理以形成元件隔离区域。

15. 发明授权

US5118636A Process for forming isolation trench in ion-implanted region 失效
标题翻译：在离子植入区域形成分离固化物的方法
公开(公告)号：US5118636A
公开(公告)日：1992-06-02
申请号：US269437
申请日：1988-11-09
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L21/302 , H01L21/306 , H01L21/762 , H01L21/763
CPC分类号： H01L21/763 , H01L21/762 , H01L21/76237
摘要： A process for manufacturing a trench isolation device is mainly comprised of steps of forming a trench in an impurity ion doped region in a semiconductor substrate after the impurity ion doped region has been formed by ion implantation. The ion energy for the ion implantation is charged from a low energy level to a high energy level, or vice versa, in order to provide a uniform vertical doping profile or a graded vertical doping profile. By this method, field dope layers completely surround the trench in the trench isolation device.

16. 发明申请

US20110288885A1 MEDICAL SERVICE SUPPORT APPARATUS 有权
标题翻译：医疗服务支持设备
公开(公告)号：US20110288885A1
公开(公告)日：2011-11-24
申请号：US13091833
申请日：2011-04-21
申请人： Hiroyuki ARAKI , Takashi HOSAKA , Masakazu OMURA , Yusuke KATO , Emiko OUCHI , Ryoichi HOSOYA
发明人： Hiroyuki ARAKI , Takashi HOSAKA , Masakazu OMURA , Yusuke KATO , Emiko OUCHI , Ryoichi HOSOYA
IPC分类号： G06Q50/00
CPC分类号： G06Q50/24 , G06F19/00 , G06F19/325 , G06Q50/22 , G16H50/70
摘要： A recording unit holds a plurality of examination data including the examination date of a performed examination. A search unit extracts examination data matching a set condition, of the plurality of examination data held in the recording unit. An output unit outputs a search result by the search unit. A first narrowing unit extracts examination data in which the examination date is included within a designated first period. A reference data determination unit classifies the examination data extracted by the first narrowing unit by an examinee and determines, for every examinee, one piece of the examination data to be a reference in accordance with a predetermined rule. A second narrowing unit sets, for every examinee, a second period designated in at least one of the past direction and the future direction starting from a reference date that is the examination date of the examination data determined by the reference data determination unit and extracts examination data in which the examination date is included within the second period.
摘要翻译：记录单元保存包括执行检查的检查日期的多个检查数据。搜索单元提取与保持在记录单元中的多个检查数据相匹配的设定条件的检查数据。输出单元通过搜索单元输出搜索结果。第一缩小单元提取在指定的第一周期内包括检查日期的检查数据。参考数据确定单元将由第一变窄单元提取的检查数据分类为受检者，并且根据预定规则为每个受检者确定一个检查数据作为参考。第二缩小单元针对每个受试者设定从作为由参考数据确定单元确定的检查数据的检查日期的参考日期开始的至少一个过去方向和未来方向指定的第二时段，并且提取检查在第二期间内包含审查日期的数据。

17. 发明授权

US06475897B1 Semiconductor device and method of forming semiconductor device 有权
标题翻译：半导体器件及半导体器件的形成方法
公开(公告)号：US06475897B1
公开(公告)日：2002-11-05
申请号：US09639709
申请日：2000-08-14
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L2930
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/05001 , H01L2224/05124 , H01L2224/05147 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/1134 , H01L2224/13022 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13164 , H01L2224/16 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/0105 , H01L2224/13099 , H01L2924/013
摘要： A semiconductor device, such as an IC package, having the same size as an IC chip and having improved qualities is manufactured at a low cost by a particular manufacturing method. The semiconductor device has stepped-projection bumps bonded to electrode pads on a semiconductor substrate in which a semiconductor element is formed. A column portion and a portion in a horizontal portion of each stepped-projection bump are exposed while the other portion of the bump is covered with a protective material. When windows of the protective material corresponding to the column portions are formed, the windows are patterned by using a masking material based on a photoetching method, and the protective material is removed by etching.
摘要翻译：通过特定的制造方法以低成本制造具有与IC芯片相同尺寸并且具有改进的品质的诸如IC封装的半导体器件。半导体器件具有接合到其中形成半导体元件的半导体衬底上的电极焊盘的阶梯式凸起凸块。每个阶梯式凸起凸起的柱部分和水平部分中的一部分被暴露，而凸块的另一部分被保护材料覆盖。当形成对应于柱部分的保护材料的窗口时，通过使用基于光刻方法的掩模材料对窗口进行图案化，并且通过蚀刻去除保护材料。

18. 发明授权

US06329274B1 Method of producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06329274B1
公开(公告)日：2001-12-11
申请号：US07995325
申请日：1992-12-28
申请人： Naoto Inoue , Kenji Aoki , Takashi Hosaka
发明人： Naoto Inoue , Kenji Aoki , Takashi Hosaka
IPC分类号： H01L2128
CPC分类号： H01L21/76897 , H01L21/2254 , H01L21/28512 , H01L21/28525 , H01L21/76802
摘要： For forming electrical interlayer contact in a semiconductor device, an insulating film is formed on a first electrically conductive layer and then a contact hole is formed in the insulating film to expose a part of the first electroconductive, an activated surface of the exposed part is formed in the contact hole, a gas containing an impurity component is supplied to form an impurity adsorption film on the activated surface, and the contact hole is filled with a second electrically conductive layer which electrically contacts the first layer through the contact hole.
摘要翻译：为了在半导体器件中形成电中间层接触，在第一导电层上形成绝缘膜，然后在绝缘膜中形成接触孔以暴露第一导电部分，形成暴露部分的活化表面在接触孔中，供给包含杂质成分的气体，以在活化表面上形成杂质吸附膜，并且接触孔填充有通过接触孔与第一层电接触的第二导电层。

19. 发明授权

US5210043A Process for producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5210043A
公开(公告)日：1993-05-11
申请号：US588553
申请日：1990-09-26
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L21/265 , H01L21/225 , H01L21/28 , H01L21/285
CPC分类号： H01L21/2257 , H01L21/28518 , Y10S148/018
摘要： A process for producing a semiconductor device having a structure in which a silicide film is in contact with an impurity diffusion layer inside a semiconductor substrate through a contact hole, in that, after the formation of the silicide film, an element of the same conductivity type as that of the impurity diffusion layer is implanted by ion implantation in the vicinity of the interface between the silicide film and the impurity diffusion layer through the silicide film.
摘要翻译：一种半导体器件的制造方法，其具有通过接触孔使硅化物膜与半导体衬底内的杂质扩散层接触的结构，其中，在形成硅化物膜之后，具有相同导电型的元件通过离子注入在硅化物膜和杂质扩散层之间的界面附近通过硅化物膜注入杂质扩散层。

20. 发明授权

US5001527A Semiconductor device with thin insulation film 失效
标题翻译：具有薄绝缘膜的半导体器件
公开(公告)号：US5001527A
公开(公告)日：1991-03-19
申请号：US569375
申请日：1990-08-13
申请人： Takashi Hosaka
发明人： Takashi Hosaka
IPC分类号： H01L29/43 , H01L21/28 , H01L21/316 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8247 , H01L23/52 , H01L23/522 , H01L27/04 , H01L29/49 , H01L29/51 , H01L29/788 , H01L29/792 , H01L29/92
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/31608 , H01L28/40 , H01L29/4933 , H01L29/517 , H01L29/518
摘要： In the step of forming a thin insulation film with the thickness of less than 1,000 .ANG. on the polycide electrode and wiring after formiung the polycide electrode and wiring, a semiconductor device having preferable insulation performance and high reliability is formed by using a silicon oxide film (SiO.sub.2) formed by a chemical vapor deposition process using a dichlorosilane (SiH.sub.2 Cl.sub.2) gas and a nitrous oxide (N.sub.2 O) gas under a reduced pressure of from 0.1 mbar to 2 mbar and at a temperature from 700.degree. C. to 950.degree. C. as the insulation film.
摘要翻译：在形成多晶硅电极和布线之后，在多晶硅电极和布线上形成厚度小于1000的薄绝缘膜的步骤中，通过使用氧化硅膜（具有绝缘性能和高可靠性）形成具有优选的绝缘性能和高可靠性的半导体器件 SiO 2），其通过使用二氯硅烷（SiH 2 Cl 2）气体和一氧化二氮（N 2 O）气体在0.1mbar至2mbar的减压下和在700℃至950℃的温度下通过化学气相沉积法形成，如绝缘膜。

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