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11. 发明授权

US08189371B2 Nonvolatile semiconductor memory device and method for driving same 有权
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：US08189371B2
公开(公告)日：2012-05-29
申请号：US12851002
申请日：2010-08-05
申请人： Ryota Katsumata , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Ryota Katsumata , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： G11C11/14
CPC分类号： G11C16/0483 , G11C16/06 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a stacked body, a through-hole, a semiconductor pillar, and a charge storage film. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in the through-hole. The charge storage film is provided between the electrode films and the semiconductor pillar. Memory cells are formed at each intersection between the electrode films and the semiconductor pillar. The control circuit writs a first value to at least some of the memory cells, performs an erasing operation of the first value from the memory cell written with the first value, reads data stored in the memory cell having undergone the erasing operation, and sets the memory cell to be unusable in a case that the first value is read from the memory cell.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。存储单元阵列包括层叠体，通孔，半导体柱和电荷存储膜。层叠体包括交替层叠有多个电极膜的多个绝缘膜。通孔形成在堆叠体中以沿堆叠方向对齐。半导体柱埋在通孔中。电荷存储膜设置在电极膜和半导体柱之间。在电极膜和半导体柱之间的每个交叉处形成存储单元。控制电路将第一值写入至少部分存储单元，从写入第一值的存储单元执行第一值的擦除操作，读取存储在经过擦除操作的存储单元中的数据，并将在从存储器单元读取第一值的情况下，存储器单元不可用。

12. 发明授权

US08188530B2 Nonvolatile semiconductor memory device and method for manufacturing same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08188530B2
公开(公告)日：2012-05-29
申请号：US12728727
申请日：2010-03-22
申请人： Hiroyasu Tanaka , Ryota Katsumata , Hideaki Aochi , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Hiroyasu Tanaka , Ryota Katsumata , Hideaki Aochi , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L21/8239 , H01L29/78 , H01L27/088
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conductive layer.
摘要翻译：一种设置有单元阵列部分和外围电路部分的半导体存储器件，该器件包括：背栅电极; 设置在所述背栅电极上的层叠体; 沿层叠方向延伸的多个半导体柱; 连接构件，每个连接构件将半导体柱之一连接到另一个半导体柱; 向所述背栅电极施加电位的背栅极电极接触; 设置在所述外围电路部中的栅电极; 以及向所述栅电极，所述背栅电极和所述栅电极施加电位的栅电极接触部，分别包括：下半导体层; 设置在下半导体层上的导电层; 以及设置在所述导电层上的上半导体层，所述连接构件设置在所述上半导体层中或所述上半导体层上，所述背栅电极接触和所述栅电极接触与所述导电层接触。

13. 发明申请

US20110075481A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110075481A1
公开(公告)日：2011-03-31
申请号：US12694677
申请日：2010-01-27
申请人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Tomoko Fujiwara , Megumi Ishiduki , Yosuke Komori , Yoshimasa Mikajiri , Shigeto Oota , Ryouhei Kirisawa , Hideaki Aochi
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Tomoko Fujiwara , Megumi Ishiduki , Yosuke Komori , Yoshimasa Mikajiri , Shigeto Oota , Ryouhei Kirisawa , Hideaki Aochi
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C11/34 , G11C5/02 , G11C16/26
摘要： A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control a read operation. A plurality of the memory strings connected to one bit line via a plurality of the first select transistors. During reading of data from a selected one of the memory strings, the control circuit renders conductive the first select transistor connected to an unselected one of the memory strings and renders non-conductive the second select transistor connected to unselected one of the memory strings.
摘要翻译：非易失性半导体存储器件包括：位线; 源线; 具有串联连接的多个电数据可重写存储晶体管的存储器串; 设置在存储器串的一端和位线之间的第一选择晶体管; 设置在存储器串的另一端与源极线之间的第二选择晶体管; 以及控制电路，被配置为控制读取操作。经由多个第一选择晶体管连接到一个位线的多个存储器串。在从选择的一个存储器串读取数据期间，控制电路使连接到未选择的一个存储器串的第一选择晶体管导通，并且使第二选择晶体管连接到未选择的一个存储器串。

14. 发明申请

US20110049608A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110049608A1
公开(公告)日：2011-03-03
申请号：US12723981
申请日：2010-03-15
申请人： Masaru KIDOH , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Masaru KIDOH , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/66833 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A memory string comprises: a first semiconductor layer including a columnar portion extending in a stacking direction on a substrate; a first charge storage layer surrounding the columnar portion; and a plurality of first conductive layers stacked on the substrate so as to surround the first charge storage layer. A select transistor comprises: a second semiconductor layer in contact with an upper surface of the columnar portion and extending in the stacking direction; a second charge storage layer surrounding the second semiconductor layer; and a second conductive layer deposited above the first conductive layer to surround the second charge storage layer. The second charge storage layer is formed from a layer downward of the second conductive layer to an upper end vicinity of the second conductive layer, and is not formed in a layer upward of the upper end vicinity.
摘要翻译：存储器串包括：第一半导体层，包括在基板上沿堆叠方向延伸的柱状部分; 围绕所述柱状部分的第一电荷存储层; 以及堆叠在所述基板上以围绕所述第一电荷存储层的多个第一导电层。选择晶体管包括：与柱状部分的上表面接触并沿堆叠方向延伸的第二半导体层; 围绕所述第二半导体层的第二电荷存储层; 以及沉积在所述第一导电层上方以围绕所述第二电荷存储层的第二导电层。第二电荷存储层由第二导电层向下的层向第二导电层的上端附近形成，并且不形成在上端附近的上方。

15. 发明申请

US20100320526A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100320526A1
公开(公告)日：2010-12-23
申请号：US12727730
申请日：2010-03-19
申请人： Masaru KIDOH , Ryota KATSUMATA , Masaru KITO , Yoshiaki FUKUZUMI , Hiroyasu TANAKA , Yosuke KOMORI , Megumi ISHIDUKI , Tomoko FUJIWARA , Yoshimasa MIKAJIRI , Shigeto OOTA , Hideaki AOCHI , Ryouhei KIRISAWA , Junya MATSUNAMI
发明人： Masaru KIDOH , Ryota KATSUMATA , Masaru KITO , Yoshiaki FUKUZUMI , Hiroyasu TANAKA , Yosuke KOMORI , Megumi ISHIDUKI , Tomoko FUJIWARA , Yoshimasa MIKAJIRI , Shigeto OOTA , Hideaki AOCHI , Ryouhei KIRISAWA , Junya MATSUNAMI
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11578 , H01L23/522 , H01L23/53257 , H01L23/53271 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a memory unit; and a circuit unit provided between the semiconductor substrate and the memory unit. The memory unit includes: a stacked structural unit having electrode films alternately stacked with inter-electrode-film insulating films; a semiconductor pillar piercing the stacked structural unit; and a storage unit provided corresponding to an intersection between the electrode films and the semiconductor pillar. The circuit unit includes first and second transistors having different conductivity type, a first interconnect, and first and second contact plugs. The first interconnect includes silicide provided on a side of the first and second transistors opposite to the semiconductor substrate. The first contact plug made of polysilicon of the first conductivity type connects the first interconnect to the first transistor. The second contact plug made of polysilicon of the second conductivity type connects the first interconnect to the second transistor.
摘要翻译：非易失性半导体存储器件包括：半导体衬底; 记忆单元以及设置在半导体衬底和存储器单元之间的电路单元。存储单元包括：层叠结构单元，其具有交替层叠有电极间绝缘膜的电极膜; 穿过堆叠结构单元的半导体柱; 以及与电极膜和半导体柱之间的交点对应地设置的存储单元。电路单元包括具有不同导电类型的第一和第二晶体管，第一互连以及第一和第二接触插塞。第一互连包括设置在与半导体衬底相对的第一和第二晶体管一侧的硅化物。由第一导电类型的多晶硅制成的第一接触插头将第一互连件连接到第一晶体管。由第二导电类型的多晶硅制成的第二接触插头将第一互连件连接到第二晶体管。

16. 再颁专利

USRE35838E Electrically erasable programmable read-only memory with NAND cell structure 失效
标题翻译：具有NAND单元结构的电可擦除可编程只读存储器
公开(公告)号：USRE35838E
公开(公告)日：1998-07-07
申请号：US430271
申请日：1995-04-28
申请人： Masaki Momodomi , Fujio Masuoka , Riichiro Shirota , Yasuo Itoh , Kazunori Ohuchi , Ryouhei Kirisawa
发明人： Masaki Momodomi , Fujio Masuoka , Riichiro Shirota , Yasuo Itoh , Kazunori Ohuchi , Ryouhei Kirisawa
IPC分类号： G11C16/16 , G11C17/00
CPC分类号： G11C16/16
摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected NAND cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.
摘要翻译：公开了具有NAND单元结构的可擦除可编程只读存储器，其具有设置在N型衬底上的存储单元。存储器单元被分成NAND单元块，每个单元块具有存储单元晶体管的串联阵列。每个晶体管具有浮置栅极，连接到字线的控制栅极和用作其源极和漏极的N型扩散层。这些半导体层形成在形成于基板的表面区域的P型阱层中。阱层用作表面击穿防止层。在数据擦除模式期间，存储在所有存储单元中的数据同时被擦除。在擦除模式之后的数据写入模式期间，当选择某个NAND单元块时，NAND单元块中的存储单元依次进行数据写入。当数据被写入所选择的NAND单元块中的某个存储单元中时，该特定存储单元的控制栅极被提供有如此高的电压，以形成强电场，以允许在浮置栅极的存储单元和阱层。因此，只能选择所选单元格。

17. 发明授权

US5597748A Method of manufacturing NAND type EEPROM 失效
标题翻译：制造NAND型EEPROM的方法
公开(公告)号：US5597748A
公开(公告)日：1997-01-28
申请号：US247589
申请日：1994-05-23
申请人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
发明人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11519 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.
摘要翻译：本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。浮动栅极部分地覆盖沟道区域。因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。多个存储单元串联连接以构成基本块。相邻的基本块由增强型MOS晶体管分开。在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

18. 发明授权

US5469444A Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels 失效
标题翻译：具有写入验证控制器的电可擦除和可编程非易失性存储器系统，使用两个参考电平
公开(公告)号：US5469444A
公开(公告)日：1995-11-21
申请号：US341955
申请日：1994-11-16
申请人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
发明人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
IPC分类号： G11C11/56 , G11C16/34 , G11C29/50 , G01R31/28
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/3404 , G11C16/3413 , G11C16/3418 , G11C16/3431 , G11C16/3459 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/0403 , G11C2211/5621
摘要： An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.
摘要翻译： EEPROM包括存储单元晶体管的阵列，其被分成每个包括串联连接的单元晶体管的NAND单元单元的单元块。读出放大器连接到位线和比较器。数据锁存电路连接到比较器，用于锁存从数据输入缓冲器提供的写入数据。在所选择的块中选择用于编程的所需单元晶体管被一次编程之后，执行写验证操作。比较器将从编程单元晶体管之一读取的实际数据与写入数据进行比较，以验证其写入状态。写验证过程使用限定允许变化范围的下限和上限的第一和第二参考电压来检查所得到的阈值电压的变化。如果使用第一电压的比较结果表明，不规则写入的单元晶体管保持不足阈值电压，其不足以落在该范围内，对于相同的单元晶体管，写操作继续进行。如果在使用第二电压的情况下的比较结果表明剩余写入过多的单元晶体管，则该块至少部分地被“保护”。

19. 发明授权

US5293337A Electrically erasable programmable read-only memory with electric field decreasing controller 失效
标题翻译：电可擦除可编程只读存储器，具有电场降低控制器
公开(公告)号：US5293337A
公开(公告)日：1994-03-08
申请号：US683733
申请日：1991-04-11
申请人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
发明人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/0483
摘要： A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.
摘要翻译： NAND单元型EEPROM具有位线，其各自与包括四个存储单元晶体管的串联阵列的NAND单元单元相关联。每个晶体管是具有控制栅极和用于数据存储的浮动栅极的MOSFET。存储单元晶体管分别在其控制栅极处连接到字线。 NAND单元单元的一端通过第一选择晶体管连接到相应的位线; 其另一端经由第二选择晶体管连接到源极电压。存储单元晶体管和选择晶体管布置在形成在衬底中的阱区中。在擦除模式中，位线电压，衬底电压和阱电压保持在高电压，而字线为零伏。选择晶体管的栅极电位被保持在高电压，由此这些选择晶体管的内部电场被削弱以改善其绝缘击穿特性。

20. 发明授权

US5050125A Electrically erasable programmable read-only memory with NAND cellstructure 失效
标题翻译：具有NAND单元结构的电可擦除可编程只读存储器
公开(公告)号：US5050125A
公开(公告)日：1991-09-17
申请号：US272404
申请日：1988-11-17
申请人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
发明人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
IPC分类号： G11C16/04 , G11C16/08 , G11C16/30 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/08 , G11C16/30
摘要： An erasable programmable read-only memory with a NAND cell structure including NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected is series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" Level voltage (approximately O V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.
摘要翻译：具有包括NAND单元块的NAND单元结构的可擦除可编程只读存储器，每个NAND单元块具有连接到相应位线的选择晶体管和连接的存储单元晶体管。字线连接到单元晶体管的控制栅极。在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。提供控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约为0V），对位于所选择的单元之间的字线或字线施加“H”电平电压（大约20V）字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入特定位线的数据相对应的电压，以及将“H”和“L”电平电压之间的中间电压施加到未选择的位线，从而通过隧道将数据写入所选择的单元。如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

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