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11. 发明授权

US07332770B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07332770B2
公开(公告)日：2008-02-19
申请号：US11192011
申请日：2005-07-29
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L29/72
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/41766 , H01L29/4238 , H01L29/66727 , H01L29/66734
摘要： A semiconductor device of this invention is a vertical power MOSFET having a plurality of first trenches where a trench gate is formed. It has a first column region of a second conductivity type placed beneath the first trenches and formed vertically in an epitaxial layer of a first conductivity type, and a second column region of the second conductivity type placed beneath a base region between the first trenches and formed vertically in the epitaxial layer of the first conductivity type. A sum of depletion charge in the first and the second column regions is substantially equal to depletion charge in the epitaxial layer of the first conductivity type.
摘要翻译：本发明的半导体器件是具有形成沟槽栅极的多个第一沟槽的垂直功率MOSFET。它具有第一导电类型的第一列区域，放置在第一沟槽的下面并垂直形成在第一导电类型的外延层中，并且第二导电类型的第二列区域位于第一沟槽之间的基极区域下方并形成垂直于第一导电类型的外延层。第一和第二列区域中的耗尽电荷之和基本上等于第一导电类型的外延层中的耗尽电荷。

12. 发明申请

US20070045700A1 Semiconductor apparatus and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070045700A1
公开(公告)日：2007-03-01
申请号：US11500332
申请日：2006-08-08
申请人： Kinya Ohtani , Kenya Kobayashi
发明人： Kinya Ohtani , Kenya Kobayashi
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095
摘要： A semiconductor apparatus according to the present invention includes a P type base diffusion layer on an N type epitaxial layer, a plurality of gate electrodes reaching to the N− epitaxial layer, an N type source diffusion layer in a region near the gate electrodes, a first P+ type diffusion layer in a region where the N type source diffusion layer is not formed, and a second P+ type diffusion layer formed separated from the first P+ type diffusion layer, deeper than the first P+ type diffusion layer, and shallower than a bottom of a trench.
摘要翻译：根据本发明的半导体装置包括在N型外延层上的P型基极扩散层，到达N外延层的多个栅电极，在栅电极附近的区域中的N型源极扩散层，在未形成N型源极扩散层的区域中的第一P +型扩散层和与第一P +型扩散层相比形成为比第一P +型扩散层更深的第二P +型扩散层，比第一P +型扩散层浅的沟渠

13. 发明申请

US20060226475A1 Vertical field effect transistor 失效
标题翻译：垂直场效应晶体管
公开(公告)号：US20060226475A1
公开(公告)日：2006-10-12
申请号：US11191929
申请日：2005-07-29
申请人： Hideo Yamamoto , Kenya Kobayashi
发明人： Hideo Yamamoto , Kenya Kobayashi
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/4238 , H01L29/456 , H01L29/66727 , H01L29/66734
摘要： A MOSFET has a base layer and a source layer in a cell surrounded by a trench gate formed in a semiconductor substrate. A trench contact is formed through the source layer and the base layer. The gate is polygonal such as square. The trench contact is thin and linear so as to increase embedding characteristics. Further, the trench contact is ring or cross shaped so as to reduce a source length.
摘要翻译： MOSFET在由半导体衬底中形成的沟槽栅包围的单元中具有基极层和源极层。通过源极层和基极层形成沟槽接触。门是多边形，如正方形。沟槽接触是薄且线性的，以增加嵌入特性。此外，沟槽接触是环形或十字形的，以便减少源长度。

14. 发明授权

US06638798B2 Method of fabricating a semiconductor device of high-voltage CMOS structure 有权
标题翻译：制造高压CMOS结构的半导体器件的方法
公开(公告)号：US06638798B2
公开(公告)日：2003-10-28
申请号：US09964393
申请日：2001-09-28
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L2100
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66659 , H01L29/7835
摘要： A transistor of a second conductivity type is of an LMOS structure, and a transistor of a first conductivity type is of an LDMOS structure. The transistor of the first conductivity type has a drain base layer which functions in the same manner as a drain offset diffusion layer and is formed in a substrate separately from a source base diffusion layer. The transistor of the first conductivity type has a stably high breakdown voltage and a low on-state resistance as with the transistor of the second conductivity type.
摘要翻译：第二导电类型的晶体管具有LMOS结构，并且第一导电类型的晶体管具有LDMOS结构。第一导电类型的晶体管具有以与漏极偏移扩散层相同的方式起作用的漏极基极层，并且与源极基底扩散层分开形成在衬底中。与第二导电类型的晶体管一样，第一导电类型的晶体管具有稳定的高击穿电压和低导通状态电阻。

15. 发明授权

US06278156B1 Dielectric separate type semiconductor device 有权
标题翻译：介质分离型半导体器件
公开(公告)号：US06278156B1
公开(公告)日：2001-08-21
申请号：US09191389
申请日：1998-11-12
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L310392
CPC分类号： H01L21/76281 , H01L21/76275 , H01L21/76283 , H01L29/7835
摘要： An SOI substrate is formed by bonding first and second semiconductor substrates of p− type through an insulating film interposed in between the substrates. In an SOI layer of a p type at the surface side of the two, a trench isolation region is formed for selecting elements so as to enclose an element forming region by burying a trench made of an oxide film. A MOS transistor having p+ type drain diffusion layer and p− type drain diffusion layer is formed in this element forming region isolated by a dielectric region. A same potential is applied to an electrode connected to the p+ diffusion layer provided outside of the element forming region enclosed by the trench isolation region, and the drain diffusion layer. As a result, without forming an electrode on the back side of the SOI substrate, deterioration of withstand voltage of elements can be prevented.
摘要翻译：通过将介于基板之间的绝缘膜接合p型的第一和第二半导体衬底而形成SOI衬底。在两个表面侧的p型SOI层中，形成用于选择元件的沟槽隔离区，以便通过埋入由氧化膜制成的沟槽来包围元件形成区域。在由电介质区域隔离的元件形成区域中形成具有p +型漏极扩散层和p型漏极扩散层的MOS晶体管。与设置在由沟槽隔离区域包围的元件形成区域外部的p +扩散层连接的电极和漏极扩散层也施加相同的电位。结果，在SOI衬底的背侧不形成电极，可以防止元件的耐受电压劣化。

16. 发明授权

US5858855A Semiconductor substrate, process for production thereof, and semiconductor device 失效
标题翻译：半导体衬底，其制造方法和半导体器件
公开(公告)号：US5858855A
公开(公告)日：1999-01-12
申请号：US874737
申请日：1997-06-13
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L29/744 , H01L21/02 , H01L21/332 , H01L21/336 , H01L21/762 , H01L29/739 , H01L29/74 , H01L29/78 , H01L21/76
CPC分类号： H01L21/76251
摘要： The present invention relates to a semiconductor substrate which is a composite substrate obtained by (1) forming, on one side of a first single-crystal silicon substrate of first conductivity and low impurity content, a polycrystalline silicon layer of first conductivity and higher impurity content than the impurity content of the first single-crystal silicon substrate, which layer later becomes a life-time killer of a second-conductivity carrier, (2) bonding, on the polycrystalline silicon layer, a second single-crystal silicon substrate of second conductivity and high impurity content, and (3) subjecting the resulting bonded wafer to a heat treatment, as well as to a process for production of the semiconductor substrate. The present invention relates particularly to a semiconductor substrate useful for formation of a vertical power semiconductor device and a process for production of the semiconductor substrate. The present invention relates also to a semiconductor device obtained using the above semiconductor substrate.
摘要翻译：本发明涉及一种半导体衬底，其是通过（1）在第一导电性和低杂质含量的第一单晶硅衬底的一侧上形成具有第一导电性和较高杂质含量的多晶硅层而获得的复合衬底比第一单晶硅衬底的杂质含量高，这一层后来成为第二导电载体的终身杀伤剂，（2）在多晶硅层上键合具有第二导电性的第二单晶硅衬底杂质含量高，（3）对所得到的接合晶片进行热处理，以及制造半导体基板的工序。本发明特别涉及可用于形成垂直功率半导体器件的半导体衬底和用于制造半导体衬底的工艺。本发明还涉及使用上述半导体衬底获得的半导体器件。

17. 发明授权

US5691231A Method of manufacturing silicon on insulating substrate 失效
标题翻译：在绝缘基板上制造硅的方法
公开(公告)号：US5691231A
公开(公告)日：1997-11-25
申请号：US779226
申请日：1997-01-07
申请人： Kenya Kobayashi , Tomohiro Hamajima , Kensuke Okonogi
发明人： Kenya Kobayashi , Tomohiro Hamajima , Kensuke Okonogi
IPC分类号： H01L21/20 , H01L21/762 , H01L21/76
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76286 , Y10S148/012
摘要： A first silicon single crystal substrate and a second silicon single crystal substrate are bonded together and the first silicon single crystal substrate is formed thin as an SOI layer. An insulation film is buried in portions of the bonding surface of one of the two silicon single crystal substrates, and in addition, a polycrystal silicon layer is formed on the bonding surface of the silicon single crystal substrate on the side into which the insulation film is buried.
摘要翻译：第一硅单晶衬底和第二硅单晶衬底被结合在一起，并且第一硅单晶衬底被形成为薄的SOI层。在两个硅单晶衬底之一的接合表面的部分中埋设有绝缘膜，此外，在单晶硅衬底的绝缘膜的一侧的接合面上形成多晶硅层埋葬

18. 发明授权

US08361865B2 Method of manufacturing a semiconductor device having vertical MOSFET 失效
标题翻译：制造具有垂直MOSFET的半导体器件的方法
公开(公告)号：US08361865B2
公开(公告)日：2013-01-29
申请号：US12926678
申请日：2010-12-03
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L29/0615 , H01L29/0638 , H01L29/0653 , H01L29/402 , H01L29/41766 , H01L29/4238 , H01L29/456 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L2224/0401 , H01L2224/05558 , H01L2224/05572 , H01L2224/0603 , H01L2224/06051 , H01L2224/13021 , H01L2224/131 , H01L2224/1411 , H01L2224/14131 , H01L2224/16 , H01L2924/0002 , H01L2924/04941 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/00014 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device, includes forming a first trench and a second trench in a semiconductor region of a first conductivity type simultaneously, forming a gate insulating film and a gate electrode in the first trench, forming a channel region of a second conductivity type in the semiconductor region, forming a source region of the first conductivity type in the channel region, forming a diffusion region of the first conductivity type which has a higher concentration than that of the semiconductor region in a part of the semiconductor region located immediately under the second trench by implanting impurity ions of the first conductivity type through the second trench, and forming a drain electrode in a part of the second trench.
摘要翻译：一种制造半导体器件的方法，包括在第一导电类型的半导体区域中同时形成第一沟槽和第二沟槽，在第一沟槽中形成栅极绝缘膜和栅电极，形成第二导电性的沟道区在半导体区域中形成沟道区域中的第一导电类型的源极区域，形成第一导电类型的扩散区域，其具有比位于半导体区域的半导体区域的半导体区域的半导体区域的半导体区域的一部分的浓度更高的浓度所述第二沟槽通过所述第二沟槽注入所述第一导电类型的杂质离子，以及在所述第二沟槽的一部分中形成漏电极。

19. 发明授权

US08314460B2 Vertical power MOSFET semiconductor apparatus having separate base regions and manufacturing method thereof 有权
标题翻译：具有分离的基极区域的垂直功率MOSFET半导体器件及其制造方法
公开(公告)号：US08314460B2
公开(公告)日：2012-11-20
申请号：US12585381
申请日：2009-09-14
申请人： Kinya Ohtani , Kenya Kobayashi
发明人： Kinya Ohtani , Kenya Kobayashi
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095
摘要： A semiconductor apparatus according to the present invention includes a first semiconductor layer of a first conductive type, a low concentration base region of a second conductive type formed on the first semiconductor layer, a gate electrode formed in a trench with insulating film on an inner surface of the trench that is formed to reach the first semiconductor layer from a surface of the low concentration base region, a source region of the first conductive type formed, contacting the insulating film, on a surface of the low concentration base region, a first high concentration base region, a second high concentration base region provided below and separated from the first concentration base region, and a third high concentration base region of the second conductive type included inside the low concentration base region, provided below and separated from the second high concentration base region.
摘要翻译：根据本发明的半导体装置包括第一导电类型的第一半导体层，形成在第一半导体层上的第二导电类型的低浓度基区，在内表面上形成有绝缘膜的沟槽中的栅电极形成为从低浓度基区的表面到达第一半导体层的沟槽，在低浓度基区的表面上形成与绝缘膜接触的第一导电类型的源区，第一高浓度基区，设置在第一浓度基区的下方并与第一浓度基区隔开的第二高浓度碱基区域，以及低浓度碱基区域内的第二导电型第三高浓度碱基区域，其设置在第二高浓度基地区。

20. 发明申请

US20120043604A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20120043604A1
公开(公告)日：2012-02-23
申请号：US13317781
申请日：2011-10-28
申请人： Yoshimitsu MURASE , Kenya KOBAYASHI , Hideo YAMAMOTO , Atsushi KANEKO
发明人： Yoshimitsu MURASE , Kenya KOBAYASHI , Hideo YAMAMOTO , Atsushi KANEKO
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/66734
摘要： A semiconductor device includes a semiconductor layer, a first diffused region formed in the semiconductor layer, a second diffused region formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode disposed in the trench, a top surface of the gate electrode being lower than a top surface of the semiconductor layer and sagging downwards in a center thereof, a non-doped silicate glass film disposed in the trench and formed over the gate electrode, a top surface of the silicate glass film sagging downwards in a center thereof, an oxide film disposed in the trench and formed over the non-doped silicate glass film, a top surface of the oxide film sagging downwards in a center, and a source electrode formed over the semiconductor layer so that the source electrode contacts the first and second diffusion regions, and the oxide film at the top surface thereof.
摘要翻译：半导体器件包括半导体层，形成在半导体层中的第一扩散区域，形成在第一扩散区域中的第二扩散区域，形成在半导体层中的沟槽，设置在沟槽中的栅极电极，栅电极低于半导体层的顶表面并且在其中心向下流动，设置在沟槽中并形成在栅电极上的未掺杂硅酸盐玻璃膜，硅酸盐玻璃膜的顶表面向下垂下中心，设置在沟槽中并形成在非掺杂硅酸盐玻璃膜上的氧化物膜，氧化膜在中心向下垂的顶表面和形成在半导体层上的源电极，使得源电极接触第一和第二扩散区，以及其顶表面处的氧化物膜。

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