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11. 发明授权

US06180463B2 Method for fabricating a multi-level mask ROM 失效
标题翻译：多级掩模ROM的制造方法
公开(公告)号：US06180463B2
公开(公告)日：2001-01-30
申请号：US09182013
申请日：1998-10-29
申请人： Kazutaka Otsuki
发明人： Kazutaka Otsuki
IPC分类号： H01L218236
CPC分类号： H01L27/11233 , H01L27/1126
摘要： A method for fabricating a multi-level mask ROM includes the steps of forming a plurality of memory cell transistors, depositing and planarizing a dielectric film covering the memory cell transistors, forming an opening in the dielectric film in the area for a selected memory cell transistor, and injecting impurity ions through the opening and the gate electrode of the selected memory cell transistor into the channel area thereof to obtain a desired threshold voltage. Planarization of the dielectric film reduces scattering of the injected ions, thereby preventing transverse extension of the injected ions and achieving a higher integration of the multi-level mask ROM.
摘要翻译：一种制造多电平掩膜ROM的方法包括以下步骤：形成多个存储单元晶体管，沉积和平坦化覆盖存储单元晶体管的电介质膜，在所选择的存储单元晶体管的区域中形成电介质膜的开口并且通过所选存储单元晶体管的开口和栅电极将杂质离子注入其沟道区域以获得期望的阈值电压。电介质膜的平面化减少注入的离子的散射，从而防止注入的离子的横向延伸并实现多电平掩模ROM的更高的集成。

12. 发明授权

US08562850B2 Emulsion for vibration damping materials 有权
标题翻译：用于减震材料的乳液
公开(公告)号：US08562850B2
公开(公告)日：2013-10-22
申请号：US12057928
申请日：2008-03-28
申请人： Yukihiro Miyawaki , Kazutaka Otsuki , Dai Nagaishi , Takahiro Miwa
发明人： Yukihiro Miyawaki , Kazutaka Otsuki , Dai Nagaishi , Takahiro Miwa
IPC分类号： E04B1/82 , C08L33/06
CPC分类号： C08F2/26 , C08F257/02 , C09D5/02
摘要： The present invention relates to an emulsion for vibration damping materials, including an emulsion obtainable by emulsion polymerization of a monomer component, wherein the emulsion is obtainable by emulsion polymerization using an anionic emulsifier and/or a reactive emulsifier, and emulsion particles have an average particle diameter of 100 to 450 nm, and an emulsion for vibration damping materials, comprising acrylic emulsion particles each having a core part and a shell part, wherein the acrylic emulsion particles are obtainable by polymerizing a monomer component including a monomer having a Q value of 0.6 to 1.4 and an e value of −0.4 to −1.2.
摘要翻译：本发明涉及一种用于减振材料的乳液，其包括可通过单体组分的乳液聚合获得的乳液，其中乳液可通过使用阴离子乳化剂和/或反应性乳化剂的乳液聚合获得，乳液颗粒具有平均颗粒 100〜450nm的直径，以及用于减震材料的乳液，其包含各自具有核心部分和壳部分的丙烯酸乳液颗粒，其中所述丙烯酸乳液颗粒可通过使包含Q值为0.6的单体的单体组分聚合而获得至1.4，e值为-0.4至-1.2。

13. 发明授权

US07642625B2 Method of evaluating thermal stress resistance of semiconductor device, and semiconductor wafer having test element 有权
标题翻译：评价半导体装置的耐热应力的方法以及具有测试元件的半导体晶片
公开(公告)号：US07642625B2
公开(公告)日：2010-01-05
申请号：US12139717
申请日：2008-06-16
申请人： Kazutaka Otsuki
发明人： Kazutaka Otsuki
IPC分类号： H01L23/544 , H01L29/10
CPC分类号： H01L22/14 , G01R31/2874 , G01R31/2884 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A thermal stress resistance evaluating method of a semiconductor device includes: forming a test circuit on a corner of each of unit regions arranged on a wafer in an array arrangement; forming a TEG chip by dicing a TEG chip region which is determined by grouping at least two of the unit regions in a predetermined shape; assembling a packaged TEG chip from the TEG chip; and executing a temperature cycling test on the packaged TEG chip by using the test circuit on the TEG chip. According to such a configuration, by adjusting the predetermined shape, the packaged TEG chip of various sizes can be formed in accordance with the design of the product chip size.
摘要翻译：半导体器件的耐热应力评估方法包括：在阵列布置中在布置在晶片上的每个单元区域的角上形成测试电路; 通过切割通过将至少两个所述单位区域分组成预定形状而确定的TEG芯片区域来形成TEG芯片; 从TEG芯片组装封装的TEG芯片; 并通过使用TEG芯片上的测试电路对封装的TEG芯片执行温度循环测试。根据这样的结构，通过调整规定的形状，可以根据产品芯片尺寸的设计形成各种尺寸的封装的TEG芯片。

14. 发明申请

US20060038233A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060038233A1
公开(公告)日：2006-02-23
申请号：US11205179
申请日：2005-08-17
申请人： Kazutaka Otsuki
发明人： Kazutaka Otsuki
IPC分类号： H01L29/76
CPC分类号： H01L21/28123 , H01L29/78 , H01L29/7831
摘要： A semiconductor device has a substrate, a first gate electrode, and a second gate electrode. The substrate has an active region surrounded by an isolation region. The first gate electrode is formed on the active region through a gate insulating film. The second gate electrode is formed on the gate insulating film such that the second gate electrode overlaps at least a part of a boundary between the active region and the isolation region. The first gate electrode and the second gate electrode are separated from each other.
摘要翻译：半导体器件具有衬底，第一栅电极和第二栅电极。衬底具有由隔离区域包围的有源区域。第一栅电极通过栅极绝缘膜形成在有源区上。第二栅极形成在栅极绝缘膜上，使得第二栅电极与有源区和隔离区之间的边界的至少一部分重叠。第一栅极电极和第二栅极电极彼此分离。

15. 发明授权

US06177693B1 Semiconductor device 有权
标题翻译：半导体器件使用虚拟图案来保留图案密度
公开(公告)号：US06177693B1
公开(公告)日：2001-01-23
申请号：US09162886
申请日：1998-09-30
申请人： Kazutaka Otsuki
发明人： Kazutaka Otsuki
IPC分类号： H01L27108
CPC分类号： H01L27/11253 , H01L27/0207 , H01L27/105 , H01L27/112 , H01L27/11293 , Y10S257/908 , Y10S257/909
摘要： In a memory cell section of a memory cell array in a semiconductor memory, N+ diffused layers and gate electrode conductors are located with the same line width and with an equal spacing. In a selector section, the N+ diffused layers and the gate electrode conductors are not located with an equal spacing. However, a dummy N+ diffused layer is added to an end of the N+ diffused layer in the selector section. In addition, a dummy N+ diffused layer is additionally located in a region which had existed as an empty region corresponding to the N+ diffused layer in the memory cell section. Thus, a resist pattern for the N+ diffused layers is formed as a designed pattern, and the characteristics of memory cell transistors or selector transistors is homogenized.
摘要翻译：在半导体存储器中的存储单元阵列的存储单元部分中，N +扩散层和栅极电极导体以相同的线宽和等间距定位。在选择器部分中，N +扩散层和栅电极导体不是以相等的间距定位。然而，在选择器部分中的N +扩散层的一端添加虚拟N +扩散层。此外，虚拟N +扩散层另外位于存储单元部分中与N +扩散层对应的空区域的区域中。因此，形成用于N +扩散层的抗蚀剂图案作为设计图案，并且存储单元晶体管或选择晶体管的特性被均匀化。

16. 发明授权

US08441076B2 SRAM 失效
公开(公告)号：US08441076B2
公开(公告)日：2013-05-14
申请号：US13100745
申请日：2011-05-04
申请人： Kazutaka Otsuki , Jun-ichi Takizawa
发明人： Kazutaka Otsuki , Jun-ichi Takizawa
IPC分类号： H01L31/119
CPC分类号： H01L27/1104 , H01L27/11
摘要： An exemplary aspect of the present invention is an SRAM including: a first gate electrode that constitutes a first load transistor; a second gate electrode that extends in a longitudinal direction of the first gate electrode so as to be spaced apart from the first gate electrode, and constitutes a first drive transistor; a third gate electrode that extends in parallel to the first gate electrode, and constitutes a second load transistor; a first p-type diffusion region that is formed so as to intersect with the third gate electrode, and constitutes the second load transistor; and a first shared contact formed over the first and second gate electrodes and the first p-type diffusion region. The first p-type diffusion region extends to the vicinity of a first gap region between the first and second gate electrodes, and is not formed in the first gap region.
摘要翻译：本发明的示例性方面是一种SRAM，包括：构成第一负载晶体管的第一栅电极; 第二栅电极，其沿着所述第一栅电极的纵向方向延伸以与所述第一栅电极间隔开，并构成第一驱动晶体管; 第三栅电极，其平行于所述第一栅电极延伸，并构成第二负载晶体管; 形成为与第三栅电极交叉的第一p型扩散区，构成第二负载晶体管; 以及形成在第一和第二栅极电极和第一p型扩散区域上的第一共享接触。第一p型扩散区域延伸到第一和第二栅电极之间的第一间隙区域附近，并且不形成在第一间隙区域中。

17. 发明申请

US20080308800A1 METHOD OF EVALUATING THERMAL STRESS RESISTANCE OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR WAFER HAVING TEST ELEMENT 有权
标题翻译：评估半导体器件的耐热应力的方法和具有测试元件的半导体波长
公开(公告)号：US20080308800A1
公开(公告)日：2008-12-18
申请号：US12139717
申请日：2008-06-16
申请人： Kazutaka OTSUKI
发明人： Kazutaka OTSUKI
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/14 , G01R31/2874 , G01R31/2884 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A thermal stress resistance evaluating method of a semiconductor device includes: forming a test circuit on a corner of each of unit regions arranged on a wafer in an array arrangement; forming a TEG chip by dicing a TEG chip region which is determined by grouping at least two of the unit regions in a predetermined shape; assembling a packaged TEG chip from the TEG chip; and executing a temperature cycling test on the packaged TEG chip by using the test circuit on the TEG chip. According to such a configuration, by adjusting the predetermined shape, the packaged TEG chip of various sizes can be formed in accordance with the design of the product chip size.
摘要翻译：半导体器件的耐热应力评估方法包括：在阵列布置中在布置在晶片上的每个单元区域的角上形成测试电路; 通过切割通过将至少两个所述单位区域分组成预定形状而确定的TEG芯片区域来形成TEG芯片; 从TEG芯片组装封装的TEG芯片; 并通过使用TEG芯片上的测试电路对封装的TEG芯片执行温度循环测试。根据这样的结构，通过调整规定的形状，可以根据产品芯片尺寸的设计形成各种尺寸的封装的TEG芯片。

18. 发明授权

US06436772B2 Method of manufacturing semiconductor device having memory cell transistors 失效
标题翻译：制造具有存储单元晶体管的半导体器件的方法
公开(公告)号：US06436772B2
公开(公告)日：2002-08-20
申请号：US09875050
申请日：2001-06-07
申请人： Kazutaka Otsuki
发明人： Kazutaka Otsuki
IPC分类号： H01L218236
CPC分类号： H01L27/1126 , H01L21/266 , H01L27/112 , H01L27/11531 , Y10S438/923
摘要： A plurality of diffusion layers extending in a first direction is formed at a surface of a semiconductor substrate in a cell region to be provided with the memory cell transistors. A plurality of gate electrodes extending in a second direction perpendicular to the first direction is formed on the semiconductor substrate in the cell regions. An interlayer insulating film is formed on the semiconductor substrate. A first resist film is formed on the interlayer insulating film. The first resist film is provided with openings in positions in alignment with regions between adjacent diffusion layers among the plurality of diffusion layers. a second resist film provided with openings previously designed in an arbitrary manner is formed on the first resist film. Then ions are implanted in the cell region using the first and second resist films as a mask.
摘要翻译：在单元区域中的半导体衬底的表面上形成有沿第一方向延伸的多个扩散层，以提供存储单元晶体管。在电池区域中的半导体衬底上形成有沿垂直于第一方向的第二方向延伸的多个栅电极。在半导体基板上形成层间绝缘膜。在层间绝缘膜上形成第一抗蚀剂膜。第一抗蚀剂膜在多个扩散层中设置有与相邻扩散层之间的区域对准的位置的开口。在第一抗蚀剂膜上形成设置有任意设计的开口的第二抗蚀剂膜。然后使用第一和第二抗蚀剂膜作为掩模将离子注入单元区域。

19. 发明授权

US06204540B1 Memory cell structure of a mask programmable read only memory with ion-implantation stopper films 失效
标题翻译：具有离子注入阻挡膜的掩模可编程只读存储器的存储单元结构
公开(公告)号：US06204540B1
公开(公告)日：2001-03-20
申请号：US09333992
申请日：1999-06-16
申请人： Kazutaka Otsuki
发明人： Kazutaka Otsuki
IPC分类号： H01L27112
CPC分类号： H01L27/112 , H01L27/1126
摘要： A semiconductor structure includes a semiconductor active region of a first conductivity type including a channel region and a non-channel region surrounding the channel region; an insulation film extending over at least the channel region; at least a control electrode on the insulation film for applying an electric field to the channel region; at least a first diffusion region of the first conductivity type occupying the channel region for defining a threshold voltage of the channel region; and at least an ion-implantation stopper film covering at least a part of the non-channel region but not covering at least a center region of the control electrode, and the ion-implantation stopper film being made of a material preventing ions from penetrating the ion-implantation stopper film in an ion-implantation for forming the first diffusion region.
摘要翻译：半导体结构包括第一导电类型的半导体有源区，包括沟道区和围绕沟道区的非沟道区; 至少在所述通道区域延伸的绝缘膜; 所述绝缘膜上至少设置有用于向所述沟道区域施加电场的控制电极; 至少第一导电类型的第一扩散区域占据沟道区域，用于限定沟道区域的阈值电压; 以及至少覆盖所述非沟道区域的至少一部分但不覆盖所述控制电极的至少中心区域的离子注入阻挡膜，所述离子注入阻挡膜由防止离子渗透的物质构成用于形成第一扩散区域的离子注入中的离子注入阻挡膜。

20. 发明授权

US5593904A Method for manufacturing NAND type semiconductor memory device 失效
标题翻译：用于制造NAND型半导体存储器件的方法
公开(公告)号：US5593904A
公开(公告)日：1997-01-14
申请号：US451548
申请日：1995-05-26
申请人： Teiichiro Nishizaka , Kazutaka Otsuki
发明人： Teiichiro Nishizaka , Kazutaka Otsuki
IPC分类号： H01L21/8246 , H01L27/112
CPC分类号： H01L27/1126 , H01L27/112
摘要： A plurality of gate electrodes are formed over a semiconductor substrate of a first conductivity type, and impurities of a second conductivity type are introduced into the substrate with a mask of the gate electrodes, to form source/drain impurity regions. Then, an insulating pattern is formed on the gate electrode and the source/drain impurity regions, and impurities of the second conductivity type are introduced into the substrate with a mask of the insulating pattern, to form a deep base region which is connected to one of the source/drain impurity regions. Also, impurities of the first conductivity type are introduced into the substrate with a mask of the insulating pattern, to form a shallow emitter region.
摘要翻译：在第一导电类型的半导体衬底上形成多个栅电极，并且用栅电极的掩模将第二导电类型的杂质引入到衬底中，以形成源/漏杂质区。然后，在栅电极和源极/漏极杂质区上形成绝缘图案，并且用绝缘图案的掩模将第二导电类型的杂质引入到衬底中，以形成连接到绝缘图案的深基区的源极/漏极杂质区域。此外，第一导电类型的杂质用绝缘图案的掩模引入到衬底中，以形成浅的发射极区域。

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