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1. 发明申请

US20110278677A1 SRAM 失效
公开(公告)号：US20110278677A1
公开(公告)日：2011-11-17
申请号：US13100745
申请日：2011-05-04
申请人： Kazutaka OTSUKI , Jun-ichi TAKIZAWA
发明人： Kazutaka OTSUKI , Jun-ichi TAKIZAWA
IPC分类号： H01L27/092
CPC分类号： H01L27/1104 , H01L27/11
摘要： An exemplary aspect of the present invention is an SRAM including: a first gate electrode that constitutes a first load transistor; a second gate electrode that extends in a longitudinal direction of the first gate electrode so as to be spaced apart from the first gate electrode, and constitutes a first drive transistor; a third gate electrode that extends in parallel to the first gate electrode, and constitutes a second load transistor; a first p-type diffusion region that is formed so as to intersect with the third gate electrode, and constitutes the second load transistor; and a first shared contact formed over the first and second gate electrodes and the first p-type diffusion region. The first p-type diffusion region extends to the vicinity of a first gap region between the first and second gate electrodes, and is not formed in the first gap region.
摘要翻译：本发明的示例性方面是一种SRAM，包括：构成第一负载晶体管的第一栅电极; 第二栅电极，其沿着所述第一栅电极的纵向方向延伸以与所述第一栅电极间隔开，并构成第一驱动晶体管; 第三栅电极，其平行于所述第一栅电极延伸，并构成第二负载晶体管; 形成为与第三栅电极交叉的第一p型扩散区，构成第二负载晶体管; 以及形成在第一和第二栅极电极和第一p型扩散区域上的第一共享接触。第一p型扩散区域延伸到第一和第二栅电极之间的第一间隙区域附近，并且不形成在第一间隙区域中。

2. 发明授权

US07279376B2 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07279376B2
公开(公告)日：2007-10-09
申请号：US10998947
申请日：2004-11-30
申请人： Kazutaka Otsuki
发明人： Kazutaka Otsuki
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： The present invention provides a technology for forming the trenches having different depths in one semiconductor substrate, which enables easily conducting the photo resist process employed for the etch process and forming trenches at higher depth dimension accuracy. The openings of the first films are formed in the semiconductor substrate to expose surfaces of the semiconductor substrate, the semiconductor substrate is etched through the openings to a depth of the shallower trench and then the cell region is covered with the second photo resist pattern, and the peripheral region is etched through the first films to form the deeper trench. Since the etch process is conducted under the conditions, in which the surfaces of the semiconductor substrate are exposed (opened) within the openings in the first film, trenches having different depths can be formed with higher depth dimension accuracy by suitably controlling the etch conditions.
摘要翻译：本发明提供一种用于在一个半导体衬底中形成具有不同深度的沟槽的技术，其能够容易地传导用于蚀刻工艺的光刻胶工艺并以更高的深度尺寸精度形成沟槽。第一膜的开口形成在半导体衬底中以暴露半导体衬底的表面，半导体衬底通过开口蚀刻到较浅沟槽的深度，然后电池区域被第二光刻胶图案覆盖，以及通过第一膜蚀刻外围区域以形成更深的沟槽。由于蚀刻工艺是在半导体衬底的表面在第一膜的开口内露出（打开）的条件下进行的，因此通过适当地控制蚀刻条件，可以以更高的深度尺寸精度形成具有不同深度的沟槽。

3. 发明申请

US20070090526A1 Semiconductor device that attains a high integration 审中-公开
标题翻译：实现高集成度的半导体器件
公开(公告)号：US20070090526A1
公开(公告)日：2007-04-26
申请号：US11585205
申请日：2006-10-24
申请人： Kazutaka Otsuki
发明人： Kazutaka Otsuki
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L22/32 , H01L24/03 , H01L2224/02166 , H01L2224/05093 , H01L2224/05096 , H01L2224/05599 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/13091 , H01L2924/14 , H01L2924/3025 , H01L2224/45099
摘要： A semiconductor device includes a substrate a first wiring layer and a bonding wiring layer. On the substrate, semiconductor elements are formed. The first wiring layer is laminated on the substrate. The bonding wiring layer is bondable and laminated on the first wiring layer. The first wiring layer includes a plurality of wirings and an insulating film. The plurality of wirings is arranged in parallel along a same direction. The insulating film is filled between respective the plurality of wirings in the first wiring layer such that the insulating film supports the bonding wiring layer.
摘要翻译：半导体器件包括基板，第一布线层和接合布线层。在基板上形成半导体元件。第一布线层层叠在基板上。接合布线层可接合并层压在第一布线层上。第一布线层包括多个布线和绝缘膜。多个布线沿着相同的方向平行布置。绝缘膜填充在第一布线层中的多个布线之间，使得绝缘膜支撑接合布线层。

4. 发明授权

US06417568B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06417568B1
公开(公告)日：2002-07-09
申请号：US09522908
申请日：2000-03-10
申请人： Kazutaka Otsuki
发明人： Kazutaka Otsuki
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L2224/02166 , H01L2224/05082 , H01L2224/05093 , H01L2224/05096 , H01L2224/05166 , H01L2224/05187 , H01L2224/05624 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01007 , H01L2924/04941 , H01L2924/04953 , H01L2924/00014
摘要： A polycide film is selectively formed in a bonding area of a silicon substrate. A BPSG film is formed as an interlayer insulating film comprising boron. Many contact holes are made, on the polycide film, in the BPSG film. Tungsten plugs are embedded in the contact holes. A film of titanium and a titanium compound is formed between the tungsten plugs and the aluminum film, and the BPSG film and the polycide film.
摘要翻译：在硅衬底的接合区域中选择性地形成多晶硅膜。 BPSG膜形成为包含硼的层间绝缘膜。 BPSG薄膜中的多晶硅薄膜上形成许多接触孔。钨插头嵌入接触孔中。在钨塞和铝膜之间形成钛和钛化合物的膜，以及BPSG膜和多晶硅膜。

5. 发明授权

US5625586A Semiconductor memory having a plurality of memory banks and sub-bit lines which are connected to a main bit line via MOS transistors whose gates are commonly connected to a selection line 失效
标题翻译：具有多个存储体和子位线的半导体存储器，其通过其栅极共同连接到选择线的MOS晶体管连接到主位线
公开(公告)号：US5625586A
公开(公告)日：1997-04-29
申请号：US606300
申请日：1996-02-23
申请人： Kazuyuki Yamasaki , Teiichiro Nishizaka , Kazutaka Otsuki
发明人： Kazuyuki Yamasaki , Teiichiro Nishizaka , Kazutaka Otsuki
IPC分类号： G11C16/04 , G11C11/56 , G11C17/12 , H01L27/10 , G11C17/00
CPC分类号： G11C17/126 , G11C11/56 , G11C11/5692 , G11C16/0491 , G11C16/24 , G11C7/18
摘要： In a semiconductor memory comprising one main bit line D1, a pair of main ground lines VG1 and VD2, a plurality of memory cell banks to be selectively connected to the main bit line D1 and the main ground lines VG1 and VD2, and a plurality of word lines W1 to Wn extending through the memory cell banks, each of the memory cell banks includes a plurality of wirings L1, L2, L3, L4 and L5 located in parallel to each other, and a threshold of a block selection transistor BT11 connected between the main bit line D1 and the wiring L3, is lower than that of block selection transistors BT12 and BT13 connected between the main bit line D1 and the wiring L2 and between the main bit line D1 and the wiring L4, respectively.
摘要翻译：在包括一个主位线D1，一对主地线VG1和VD2的半导体存储器中，选择性地连接到主位线D1和主地线VG1和VD2的多个存储单元组，以及多个字线W1至Wn延伸穿过存储单元组，每个存储单元组包括彼此并联的多个布线L1，L2，L3，L4和L5，并且块选择晶体管BT11的阈值连接在主位线D1和布线L3分别低于连接在主位线D1和布线L2之间以及主位线D1和布线L4之间的块选择晶体管BT12和BT13。

6. 发明授权

US5545911A Semiconductor device having mosfets formed in inherent and well regions of a semiconductor substrate 失效
标题翻译：在半导体衬底的固有和阱区中形成有半导体器件的半导体器件
公开(公告)号：US5545911A
公开(公告)日：1996-08-13
申请号：US350696
申请日：1994-12-07
申请人： Kazutaka Otsuki , Masaaki Yamada
发明人： Kazutaka Otsuki , Masaaki Yamada
IPC分类号： H01L29/78 , H01L21/336 , H01L21/74 , H01L27/08 , H01L27/088 , H01L29/10 , H01L29/76 , H01L29/80 , H01L29/94
CPC分类号： H01L29/66575 , H01L21/74 , H01L27/088 , H01L29/1083
摘要： A semiconductor device has an inherent region of the same conductivity type and the same impurity concentration as a semiconductor substrate and well regions located close to each other under a main surface of the semiconductor substrate. A field oxide film is selectively formed on the main surface. A MOSFET, termed an "undoped MOSFET," is formed in the inherent region. A carrier stop layer having a conductivity type opposite to, and an impurity concentration higher than, that of the inherent region is formed within the inherent region. The carrier stop layer extends from the bottom of the field oxide film and underlies the source/drain regions of the undoped MOSFET in spaced relationship therewith. The carrier stop layer prevents punch-through between the well region and densely diffused source/drain regions in the undoped MOSFET region, even when they are located close to each other. The present invention permits a higher density integration of elements or circuits in a semiconductor device to be achieved than is possible in the prior art.
摘要翻译：半导体器件具有与半导体衬底的主表面相邻的半导体衬底和阱区相同的导电类型和相同的杂质浓度的固有区域。在主表面上选择性地形成场氧化膜。在固有区域中形成了称为“未掺杂MOSFET”的MOSFET。在固有区域内形成具有与固有区域相反并且杂质浓度高于其固有区域的导电类型的载流子停止层。载流子停止层从场氧化物膜的底部延伸并且与未掺杂的MOSFET的源极/漏极区域在其间隔开的关系中。载体停止层即使在它们彼此靠近的位置时也防止了未掺杂的MOSFET区域中的阱区域和密集扩散的源极/漏极区域之间的穿透。本发明允许在半导体器件中实现比现有技术中可能的元件或电路更高密度的集成。

7. 发明授权

US07569887B2 C-shaped dummy gate electrode semiconductor device and method of manufacturing the same 有权
标题翻译： C形虚拟栅电极半导体器件及其制造方法
公开(公告)号：US07569887B2
公开(公告)日：2009-08-04
申请号：US11205179
申请日：2005-08-17
申请人： Kazutaka Otsuki
发明人： Kazutaka Otsuki
IPC分类号： H01L23/62
CPC分类号： H01L21/28123 , H01L29/78 , H01L29/7831
摘要： A semiconductor device has a substrate, a first gate electrode, and a second gate electrode. The substrate has an active region surrounded by an isolation region. The first gate electrode is formed on the active region through a gate insulating film. The second gate electrode is formed on the gate insulating film such that the second gate electrode overlaps at least a part of a boundary between the active region and the isolation region. The first gate electrode and the second gate electrode are separated from each other.
摘要翻译：半导体器件具有衬底，第一栅电极和第二栅电极。衬底具有由隔离区域包围的有源区域。第一栅电极通过栅极绝缘膜形成在有源区上。第二栅极形成在栅极绝缘膜上，使得第二栅电极与有源区和隔离区之间的边界的至少一部分重叠。第一栅极电极和第二栅极电极彼此分离。

8. 发明申请

US20080245989A1 EMULSION FOR VIBRATION DAMPING MATERIALS 有权
标题翻译：用于振动阻尼材料的乳液
公开(公告)号：US20080245989A1
公开(公告)日：2008-10-09
申请号：US12057928
申请日：2008-03-28
申请人： Yukihiro Miyawaki , Kazutaka Otsuki , Dai Nagaishi , Takahiro Miwa
发明人： Yukihiro Miyawaki , Kazutaka Otsuki , Dai Nagaishi , Takahiro Miwa
IPC分类号： E04B1/82
CPC分类号： C08F2/26 , C08F257/02 , C09D5/02
摘要： The present invention has an object to provide at least one of the following (1) to (3). (1) To provide the following emulsion for vibration damping materials: it is excellent in vibration damping property, drying property, and mechanical stability; it can improve skinning property of the coating film surface; and it can form an excellent coating film which hardly collapses, for example, hardly sags, even if the emulsion is coated on the vertical surface and dried by heating at a high temperature. (2) To provide the following emulsion for vibration damping materials: it is excellent in vibration damping property and thermal drying property; it is hardly changed with time; it can improve the stability or dispersibility of the composition; and it can form a coating film exhibiting excellent vibration damping property even if the emulsion is coated on an inclined object. (3) To provide the following emulsion for vibration damping materials: it includes acrylic emulsion particles each having a core part and a shell part and exhibits high vibration damping property in a wide temperature region; it is excellent in mechanical stability; and it is also excellent in storage stability at a low temperature. The present invention relates to an emulsion for vibration damping materials, including an emulsion obtainable by emulsion polymerization of a monomer component, wherein the emulsion is obtainable by emulsion polymerization using an anionic emulsifier and/or a reactive emulsifier, and emulsion particles have an average particle diameter of 100 to 450 nm, and an emulsion for vibration damping materials, comprising acrylic emulsion particles each having a core part and a shell part, wherein the acrylic emulsion particles are obtainable by polymerizing a monomer component including a monomer having a Q value of 0.6 to 1.4 and an e value of −0.4 to −1.2.
摘要翻译：本发明的目的是提供以下（1）至（3）中的至少一个。（1）为减震材料提供以下乳液：减振性能好，干燥性能好，机械稳定性好; 可以改善涂膜表面的表皮性能; 并且即使将乳液涂布在垂直面上并通过在高温下加热而干燥，也可以形成难以塌陷的优异的涂膜，例如几乎不下垂。（2）为减震材料提供以下乳液：减震性能和热干性能优异; 随着时间的推移几乎没有变化它可以提高组合物的稳定性或分散性; 并且即使将乳液涂覆在倾斜物体上，也可以形成具有优异的振动阻尼性能的涂膜。（3）为减震材料提供以下乳液：它包括丙烯酸乳液颗粒，每个丙烯酸乳液颗粒均具有核心部分和外壳部分，并且在宽温度区域表现出高振动阻尼性能; 机械稳定性好; 并且在低温下的储存稳定性也优异。本发明涉及一种用于减振材料的乳液，其包括可通过单体组分的乳液聚合获得的乳液，其中乳液可通过使用阴离子乳化剂和/或反应性乳化剂的乳液聚合获得，乳液颗粒具有平均颗粒 100〜450nm的直径，以及用于减震材料的乳液，其包含各自具有核心部分和壳部分的丙烯酸乳液颗粒，其中所述丙烯酸乳液颗粒可通过使包含Q值为0.6的单体的单体组分聚合而获得至1.4，e值为-0.4至-1.2。

9. 发明申请

US20050142808A1 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20050142808A1
公开(公告)日：2005-06-30
申请号：US10998947
申请日：2004-11-30
申请人： Kazutaka Otsuki
发明人： Kazutaka Otsuki
IPC分类号： H01L21/3065 , H01L21/76 , H01L21/762 , H01L21/768 , H01L21/8242 , H01L27/08 , H01L27/10 , H01L27/108 , H01L21/8238
CPC分类号： H01L21/76229
摘要： The present invention provides a technology for forming the trenches having different depths in one semiconductor substrate, which enables easily conducting the photo resist process employed for the etch process and forming trenches at higher depth dimension accuracy. The openings of the first films are formed in the semiconductor substrate to expose surfaces of the semiconductor substrate, the semiconductor substrate is etched through the openings to a depth of the shallower trench and then the cell region is covered with the second photo resist pattern, and the peripheral region is etched through the first films to form the deeper trench. Since the etch process is conducted under the conditions, in which the surfaces of the semiconductor substrate are exposed (opened) within the openings in the first film, trenches having different depths can be formed with higher depth dimension accuracy by suitably controlling the etch conditions.
摘要翻译：本发明提供一种用于在一个半导体衬底中形成具有不同深度的沟槽的技术，其能够容易地传导用于蚀刻工艺的光刻胶工艺并以更高的深度尺寸精度形成沟槽。第一膜的开口形成在半导体衬底中以暴露半导体衬底的表面，半导体衬底通过开口蚀刻到较浅沟槽的深度，然后电池区域被第二光刻胶图案覆盖，以及通过第一膜蚀刻外围区域以形成更深的沟槽。由于蚀刻工艺是在半导体衬底的表面在第一膜的开口内露出（打开）的条件下进行的，因此通过适当地控制蚀刻条件，可以以更高的深度尺寸精度形成具有不同深度的沟槽。

10. 发明授权

US06583492B2 Capacitor element having a contact hole structure in an electrode structure 失效
标题翻译：在电极结构中具有接触孔结构的电容器元件
公开(公告)号：US06583492B2
公开(公告)日：2003-06-24
申请号：US10254399
申请日：2002-09-25
申请人： Kazutaka Otsuki
发明人： Kazutaka Otsuki
IPC分类号： H01L2900
CPC分类号： H01L27/1203 , H01L21/76838 , H01L23/5223 , H01L27/115 , H01L28/40 , H01L29/42324 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising a first electrode and a second electrode that are formed in this order on a semiconductor substrate with an insulating layer interposed between the first and second electrodes. A contact hole is provided for connecting the second electrode to a wiring layer formed above the second electrode, the contact hole being formed at a position above a separated region of the first electrode formed separately from a main region of the first electrode.
摘要翻译：一种半导体器件，包括在半导体衬底上依次形成第一电极和第二电极，绝缘层置于第一和第二电极之间。提供接触孔，用于将第二电极连接到形成在第二电极上方的布线层，接触孔形成在与第一电极的主区域分开形成的第一电极的分离区域上方的位置处。

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