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11. 发明授权

US08258864B1 Ultra low voltage multi-stage high-speed CMOS comparator with autozeroing 有权
标题翻译：具有自动调零功能的超低压多级高速CMOS比较器
公开(公告)号：US08258864B1
公开(公告)日：2012-09-04
申请号：US13238236
申请日：2011-09-21
申请人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
发明人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
IPC分类号： H03F1/02
CPC分类号： H03F3/45183 , H03F3/45636 , H03F2200/261 , H03F2200/294 , H03F2200/453 , H03F2203/45616 , H03F2203/45628
摘要： A pre-amplifier circuit can be cascaded and drive a latch for use in a precision analog-to-digital converter (ADC). The pre-amplifier has a main section and a feedback section connected by feedback resistors that do not produce voltage drops in the main section. Offset is stored on offset capacitors during an autozeroing phase and isolated by transmission gates during an amplifying phase. The offset capacitors drive the gates of feedback transistors that drive output nodes in the main section. Autozeroing sink transistors in the feedback section operate in the linear region while current sink transistors in the main section operate in the saturated region. Kickback-charge isolation transistors may be added for charge isolation. The output may also be equalized by an equalizing transmission gate. A very low power-supply voltage is supported even for high-speed operation with offset cancellation, due to the folded feedback resistor arrangement.
摘要翻译：前级放大器电路可以级联并驱动锁存器，用于精密模数转换器（ADC）。前置放大器有一个主要部分和一个反馈部分，通过反馈电阻连接，主部分不产生电压降。偏移量在自动调零阶段存储在偏移电容上，并在放大阶段由传输门隔离。偏移电容器驱动驱动主部分中的输出节点的反馈晶体管的栅极。反馈部分中的自动归零陷波晶体管工作在线性区域，而主部分中的电流吸收晶体管工作在饱和区域。可以添加Kickback电荷隔离晶体管用于电荷隔离。输出也可以通过均衡的传输门来均衡。由于折叠的反馈电阻器布置，即使对于具有偏移消除的高速操作也支持非常低的电源电压。

12. 发明授权

US08797776B2 Diode-less full-wave rectifier for low-power on-chip AC-DC conversion 有权
标题翻译：无二极管全波整流器用于低功耗片上AC-DC转换
公开(公告)号：US08797776B2
公开(公告)日：2014-08-05
申请号：US13652474
申请日：2012-10-16
申请人： Kwok Kuen (David) Kwong , Chun Fai Wong , Leung Ling (Alan) Pun , Ho Ming (Karen) Wan
发明人： Kwok Kuen (David) Kwong , Chun Fai Wong , Leung Ling (Alan) Pun , Ho Ming (Karen) Wan
IPC分类号： H02M7/5387
CPC分类号： H02M7/219 , H02M2007/2195 , Y02B70/1408
摘要： A bridge rectifier operates on low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a transistor bridge across the A.C. inputs to produce an internal power voltage. Another four diode-connected transistors form a start-up diode bridge that generates a comparator power voltage and a reference ground. The start-up diode bridge operates even during initial start-up before the comparator and boost drivers operate. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors in the transistor bridge with voltages boosted higher than the peak A.C. voltage. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow.
摘要翻译：桥式整流器在诸如由射频识别（RFID）设备接收的低交流输入电压下工作。避免了由桥二极管引起的电压降。四个P沟道晶体管布置在跨越交流输入的晶体管桥中以产生内部电源电压。另外四个二极管连接的晶体管形成起始二极管电桥，产生比较器电源电压和参考地。在比较器和升压驱动器运行之前，起动二极管桥即使在初始启动期间也工作。比较器接收交流输入并且控制升压驱动器的定时，其交替地驱动晶体管桥中的四个p沟道晶体管的栅极，其电压升高高于峰值交流电压。基板连接到桥的电源电压一半的电源电压和桥接器的一半的交流输入，以完全关闭晶体管，防止反向电流流动。

13. 发明申请

US20140104909A1 Diode-Less Full-Wave Rectifier for Low-Power On-Chip AC-DC Conversion 有权
标题翻译：无二极管全波整流器，用于低功耗片上AC-DC转换
公开(公告)号：US20140104909A1
公开(公告)日：2014-04-17
申请号：US13652474
申请日：2012-10-16
申请人： Kwok Kuen (David) KWONG , Chun Fai WONG , Leung Ling (Alan) PUN , Ho Ming (Karen) WAN
发明人： Kwok Kuen (David) KWONG , Chun Fai WONG , Leung Ling (Alan) PUN , Ho Ming (Karen) WAN
IPC分类号： H02M7/217
CPC分类号： H02M7/219 , H02M2007/2195 , Y02B70/1408
摘要： A bridge rectifier operates on low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a transistor bridge across the A.C. inputs to produce an internal power voltage. Another four diode-connected transistors form a start-up diode bridge that generates a comparator power voltage and a reference ground. The start-up diode bridge operates even during initial start-up before the comparator and boost drivers operate. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors in the transistor bridge with voltages boosted higher than the peak A.C. voltage. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow.
摘要翻译：桥式整流器在诸如由射频识别（RFID）设备接收的低交流输入电压下工作。避免了由桥二极管引起的电压降。四个P沟道晶体管布置在跨越交流输入的晶体管桥中以产生内部电源电压。另外四个二极管连接的晶体管形成起始二极管电桥，产生比较器电源电压和参考地。在比较器和升压驱动器运行之前，起动二极管桥即使在初始启动期间也工作。比较器接收交流输入并且控制升压驱动器的定时，其交替地驱动晶体管桥中的四个p沟道晶体管的栅极，其电压升高高于峰值交流电压。基板连接到桥的电源电压一半的电源电压和桥接器的一半的交流输入，以完全关闭晶体管，防止反向电流流动。

14. 发明授权

US08471744B1 Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge 有权
标题翻译：减少残差偏移Σ-Δ模数转换器（ADC），在后沿积分相位结束时具有斩波定时
公开(公告)号：US08471744B1
公开(公告)日：2013-06-25
申请号：US13308737
申请日：2011-12-01
申请人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan
发明人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan
IPC分类号： H03M3/00
CPC分类号： H03M3/34 , H03M3/43 , H03M3/454
摘要： An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.
摘要翻译：模数转换器（ADC）具有斩波稳定的Σ-Δ调制器（SDM）。 SDM使用开关电容积分器来采样，保持和集成模拟输入以响应不重叠的多相时钟。斩波倍增器插入在第一级积分器中的运算放大器的输入和输出端。斩波器乘法器响应于不重叠的斩波时钟交换或通过差分输入。以多相时钟频率工作的主时钟被分频以触发斩波时钟的产生。延迟线确保斩波时钟的边沿在多相时钟的边沿之前发生。当多相时钟变化时，斩波倍增器已经切换并稳定，因此在由多相时钟控制的开关处的电荷注入不会被斩波乘法器立即调制。该时钟定时增加了可以在改善线性度的开关处对电荷注入进行响应的时间。

15. 发明申请

US20130076546A1 CHARGE COMPENSATION CALIBRATION FOR HIGH RESOLUTION DATA CONVERTER 有权
标题翻译：高分辨率数据转换器的电荷补偿校准
公开(公告)号：US20130076546A1
公开(公告)日：2013-03-28
申请号：US13247119
申请日：2011-09-28
申请人： Kam Chuen WAN , Yat To (William) WONG , Ho Ming (Karen) WAN , Kwai Chi CHAN
发明人： Kam Chuen WAN , Yat To (William) WONG , Ho Ming (Karen) WAN , Kwai Chi CHAN
IPC分类号： H03M1/10
CPC分类号： H03M1/1033 , H03M1/0682 , H03M1/804
摘要： A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.
摘要翻译：校准模数转换器（ADC）具有X侧阵列，其具有连接到Y侧线的X侧线和Y侧阵列的二进制加权电容器。每个阵列具有从最高有效位（MSB）到最低有效位（LSB）的二进制加权电容，但是LSB电容器被复制为终端电容器，并且上下组之间的中间电容器也被重复作为替代电容器。在校准期间，低阵列电容器切换低电平，而上电容器由X和Y阵列上的温度计代码值驱动。温度计值反转到X阵列，但在Y阵列上保持不变。测试较低的阵列位以最终确定平衡X和Y侧电压的校准值。

16. 发明申请

US20110267008A1 Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock 有权
标题翻译：使用电压升压时钟的单功率晶体管电池充电电路
公开(公告)号：US20110267008A1
公开(公告)日：2011-11-03
申请号：US13179107
申请日：2011-07-08
申请人： Kwok Kuen Kwong , Yat To Wong , Ho Ming (Karen) Wan , Chik Wai Ng
发明人： Kwok Kuen Kwong , Yat To Wong , Ho Ming (Karen) Wan , Chik Wai Ng
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译：充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。门通过由使能信号激活的开关由升压时钟驱动。使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极以截止功率晶体管。

17. 发明授权

US07999512B2 Single-power-transistor battery-charging circuit using voltage-boosted clock 有权
标题翻译：使用升压时钟的单功率晶体管电池充电电路
公开(公告)号：US07999512B2
公开(公告)日：2011-08-16
申请号：US12336514
申请日：2008-12-16
申请人： Kwok Kuen David Kwong , Yat To William Wong , Ho Ming Karen Wan , Chik Wai David Ng
发明人： Kwok Kuen David Kwong , Yat To William Wong , Ho Ming Karen Wan , Chik Wai David Ng
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译：充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。门通过由使能信号激活的开关由升压时钟驱动。使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极以截止功率晶体管。

18. 发明申请

US20100148727A1 Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock 有权
标题翻译：使用电压升压时钟的单功率晶体管电池充电电路
公开(公告)号：US20100148727A1
公开(公告)日：2010-06-17
申请号：US12336514
申请日：2008-12-16
申请人： Kwok Kuen Kwong , Yat To Wong , Ho Ming (Karen) Wan , Chik Wai Ng
发明人： Kwok Kuen Kwong , Yat To Wong , Ho Ming (Karen) Wan , Chik Wai Ng
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译：充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。门通过由使能信号激活的开关由升压时钟驱动。使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极，以关断功率晶体管。

19. 发明授权

US08643337B2 Single-power-transistor battery-charging circuit using voltage-boosted clock 有权
标题翻译：使用升压时钟的单功率晶体管电池充电电路
公开(公告)号：US08643337B2
公开(公告)日：2014-02-04
申请号：US13179107
申请日：2011-07-08
申请人： Kwok Kuen David Kwong , Yat To William Wong , Ho Ming Karen Wan , Chik Wai David Ng
发明人： Kwok Kuen David Kwong , Yat To William Wong , Ho Ming Karen Wan , Chik Wai David Ng
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译：充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。门通过由使能信号激活的开关由升压时钟驱动。使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极，以关断功率晶体管。

20. 发明授权

US07795976B2 Slew-rate-enhanced error amp with adaptive transconductance and single dominant pole shared by main and auxiliary amps 有权
标题翻译：具有自适应跨导的转换率增益误差放大器和主和辅助放大器共享的单个主导极
公开(公告)号：US07795976B2
公开(公告)日：2010-09-14
申请号：US12345862
申请日：2008-12-30
申请人： Yat To William Wong , Chik Wai David Ng , Ho Ming Karen Wan , Kam Chuen Wan , Kwok Kuen David Kwong
发明人： Yat To William Wong , Chik Wai David Ng , Ho Ming Karen Wan , Kam Chuen Wan , Kwok Kuen David Kwong
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F3/3023 , H03F3/45475 , H03F2203/45248 , H03F2203/45646 , H03F2203/45652 , H03F2203/45678
摘要： An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers.
摘要翻译：误差放大器可用于控制功率调节晶体管。误差放大器具有主放大器，上拉辅助放大器和全部驱动输出的下拉辅助放大器。输出上的补偿电容为所有放大器设置单个主极，从而提高稳定性。当差分输入具有大于有意偏移的绝对电压差时，来自辅助放大器的增加的转换电流提供高转换速率。通过调整辅助放大器的一个支路中的p沟道至n沟道晶体管比，将有意的偏移引入辅助放大器。主放大器中的源极退化电阻通过连接接收差分输入的两个差分晶体管的源极减小了供电余量并增加了线性度。串联晶体管增加了增益和输出阻抗。在放大器中没有使用正反馈的情况下，可靠性提高。

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