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11. 发明授权

US07184352B2 Memory system and method using ECC to achieve low power refresh 有权
标题翻译：使用ECC实现低功耗刷新的内存系统和方法
公开(公告)号：US07184352B2
公开(公告)日：2007-02-27
申请号：US11192971
申请日：2005-07-28
申请人： Dean A. Klein , John Schreck
发明人： Dean A. Klein , John Schreck
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G06F11/106 , G11C2211/4062
摘要： Rows of DRAM memory cells are refreshed at either a relatively high rate during normal operation or a relatively slow rate in a reduced power refresh mode. Prior to refreshing the rows of memory cells, the data are read from the memory cells, and corresponding syndromes are generated and stored. When transitioning from the reduced power refresh mode, data from the rows of memory cells are read, and the stored syndromes are used to determine if there are errors in the read data. The syndromes are also used to correct any errors that are found, and the corrected data are written to the rows of memory cells. By correcting any errors that exist when transitioning from the reduced power refresh mode, it is not necessary to use the syndromes to detect and correct errors while operating in the reduced power refresh mode.
摘要翻译： DRAM存储器单元的行在正常操作期间以相对高的速率刷新，或者在降低的功率刷新模式下刷新相对较慢的速率。在更新存储器单元的行之前，从存储器单元读取数据，并生成并存储相应的校正子。当从减小功率刷新模式转换时，读取来自存储器单元行的数据，并且使用所存储的校正子来确定读取数据中是否存在错误。综合征也用于校正发现的任何错误，并将校正的数据写入存储器单元的行。通过校正从减小功率刷新模式转换时存在的任何错误，在以降低功率刷新模式操作的情况下，不需要使用校正子来检测和校正错误。

12. 发明申请

US20060181255A1 Apparatus and methods for regulated voltage 审中-公开
标题翻译：用于调节电压的装置和方法
公开(公告)号：US20060181255A1
公开(公告)日：2006-08-17
申请号：US11059094
申请日：2005-02-15
申请人： John Schreck
发明人： John Schreck
IPC分类号： G05F1/40 , G05F1/618
CPC分类号： G05F1/618
摘要： An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide a selected voltage level. In one embodiment, the supply regulation circuit includes a reference voltage circuit connected to the supply and configured to receive a first voltage and a second voltage and provide a reference voltage and a control circuit connected to the reference voltage and configured to control the regulated voltage according to the reference voltage. The supply regulation circuit also includes an adjustment circuit controlled by the control circuit and configured to adjust the regulated voltage according to the reference voltage. The supply regulation circuit may also include a compensator circuit to provide additional adjustment to the regulated voltage.
摘要翻译：根据本发明的各个方面的电子系统包括具有调节输出以提供所选电压电平的存储器和电源调节电路。在一个实施例中，电源调节电路包括与电源连接并被配置为接收第一电压和第二电压并提供参考电压的参考电压电路和连接到参考电压的控制电路，并被配置为根据到参考电压。供电调节电路还包括由控制电路控制并被配置为根据参考电压调节调节电压的调节电路。电源调节电路还可以包括补偿电路，以对调节的电压提供额外的调整。

13. 发明授权

US06838337B2 Sense amplifier and architecture for open digit arrays 有权
标题翻译：用于开放数位数组的感应放大器和架构
公开(公告)号：US06838337B2
公开(公告)日：2005-01-04
申请号：US10267991
申请日：2002-10-10
申请人： John Schreck
发明人： John Schreck
IPC分类号： H01L21/8242 , G11C7/06 , G11C7/18 , G11C11/401 , G11C11/409 , H01L27/108 , H01L21/20 , H01L21/336
CPC分类号： G11C7/18 , G11C7/065
摘要： A method and apparatus are described which provide a memory device with sense amplifiers extending in a first direction and corresponding digit lines extending in a second direction perpendicular to the first direction. A pair of complementary digit lines may originate from different memory sub-arrays. The arrangement is particular useful for memory arrays having 6F**2 feature size.

14. 发明授权

US06721221B2 Sense amplifier and architecture for open digit arrays 有权
标题翻译：用于开放数位数组的感应放大器和架构
公开(公告)号：US06721221B2
公开(公告)日：2004-04-13
申请号：US09876095
申请日：2001-06-08
申请人： John Schreck
发明人： John Schreck
IPC分类号： G11C702
CPC分类号： G11C7/18 , G11C7/065
摘要： A method and apparatus are described which provide a memory device with sense amplifiers extending in a first direction and corresponding digit lines extending in a second direction perpendicular to the first direction. A pair of complementary digit lines may originate from different memory sub-arrays. The arrangement is particular useful for memory arrays having 6F**2 feature size.
摘要翻译：描述了一种方法和装置，其提供具有沿第一方向延伸的读出放大器的存储器件和在垂直于第一方向的第二方向上延伸的对应数字线。一对补码数字线可能来自不同的存储器子阵列。该布置对于具有6F ** 2特征尺寸的存储器阵列特别有用。

15. 发明申请

US20120155201A1 SYSTEM AND METHOD FOR HIDDEN REFRESH RATE MODIFICATION 有权
标题翻译：系统和方法用于隐藏修正率修改
公开(公告)号：US20120155201A1
公开(公告)日：2012-06-21
申请号：US13408566
申请日：2012-02-29
申请人： John Schreck , John R. Wilford
发明人： John Schreck , John R. Wilford
IPC分类号： G11C11/402 , G11C7/00
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.
摘要翻译：用于修改动态存储器单元的隐藏刷新率的系统和方法包括监视来自处理器的控制信号，并且当控制信号被断言时以第一刷新率执行动态数据的隐藏刷新。当控制信号被断言预定的持续时间时，动态数据以第二刷新率刷新。在动态存储器单元阵列的隐藏刷新期间，隐藏刷新控制器耦合到动态存储器单元阵列。隐藏刷新控制器还被配置为监视从存储器设备处的处理器识别请求的控制信号，并且在控制信号被断言时以第一刷新率刷新动态数据。所述隐藏刷新控制器还被配置为当所述控制信号被断言预定持续时间时，以第二刷新率刷新所述动态数据。

16. 发明授权

US07532532B2 System and method for hidden-refresh rate modification 有权
标题翻译：隐藏刷新率修改的系统和方法
公开(公告)号：US07532532B2
公开(公告)日：2009-05-12
申请号：US11140791
申请日：2005-05-31
申请人： John Schreck , John R. Wilford
发明人： John Schreck , John R. Wilford
IPC分类号： G11C7/00
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.
摘要翻译：用于修改动态存储器单元的隐藏刷新率的系统和方法包括监视来自处理器的控制信号，并且当控制信号被断言时以第一刷新率执行动态数据的隐藏刷新。当控制信号被断言预定的持续时间时，动态数据以第二刷新率刷新。在动态存储器单元阵列的隐藏刷新期间，隐藏刷新控制器耦合到动态存储器单元阵列。隐藏刷新控制器还被配置为监视从存储器设备处的处理器识别请求的控制信号，并且在控制信号被断言时以第一刷新率刷新动态数据。所述隐藏刷新控制器还被配置为当所述控制信号被断言预定持续时间时，以第二刷新率刷新所述动态数据。

17. 发明申请

US20050275390A1 Apparatus and methods for regulated voltage 有权
公开(公告)号：US20050275390A1
公开(公告)日：2005-12-15
申请号：US11059135
申请日：2005-02-15
申请人： John Schreck
发明人： John Schreck
IPC分类号： G05F1/46 , G05F1/40
CPC分类号： G11C5/147 , G05F1/46 , G05F1/618 , G11C11/4074
摘要： An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide a selected voltage level. In one embodiment, the supply regulation circuit includes a reference voltage circuit connected to the supply and configured to receive a first voltage and a second voltage and provide a reference voltage and a control circuit connected to the reference voltage and configured to control the regulated voltage according to the reference voltage. The supply regulation circuit also includes an adjustment circuit controlled by the control circuit and configured to adjust the regulated voltage according to the reference voltage. The supply regulation circuit may also include a compensator circuit to provide additional adjustment to the regulated voltage.

18. 发明授权

US06961272B2 Physically alternating sense amplifier activation 失效
标题翻译：物理交替感测放大器激活
公开(公告)号：US06961272B2
公开(公告)日：2005-11-01
申请号：US11046895
申请日：2005-02-01
申请人： John Schreck
发明人： John Schreck
IPC分类号： G11C7/06 , G11C7/08 , G11C11/4091
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/065
摘要： A memory device having banks of sense amplifiers comprising two types of sense amplifiers. A first driver used to activate the first type of sense amplifier is embedded into a first bank. A second driver used to activate a second type of sense amplifier is embedded into a second bank. This alternating physical placement of the first and second sense amplifier drivers within respective banks is repeated throughout the device. This alternating physical arrangement frees up the gaps and mini-gaps for other functions, reduces the buses used for sense amplifier activation signals and allows large drivers to be used, which improves the operation of the sense amplifiers and the device itself.
摘要翻译：具有包括两种类型的读出放大器的感测放大器组的存储器件。用于激活第一类型的读出放大器的第一驱动器被嵌入到第一存储体中。用于激活第二类型的读出放大器的第二驱动器被嵌入到第二存储体中。在整个设备中重复在相应组内的第一和第二读出放大器驱动器的这种交替物理放置。这种交替的物理布置释放了其他功能的间隙和微型间隙，减少了用于读出放大器激活信号的总线，并允许使用大型驱动器，从而改善了读出放大器和器件本身的工作。

19. 发明申请

US20060268643A1 System and method for hidden-refresh rate modification 有权
标题翻译：隐藏刷新率修改的系统和方法
公开(公告)号：US20060268643A1
公开(公告)日：2006-11-30
申请号：US11140791
申请日：2005-05-31
申请人： John Schreck , John Wilford
发明人： John Schreck , John Wilford
IPC分类号： G11C7/00
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of the dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to the array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at the memory device and refresh the dynamic data a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.
摘要翻译：用于修改动态存储器单元的隐藏刷新率的系统和方法包括监视来自处理器的控制信号，并且当控制信号被断言时以第一刷新率执行动态数据的隐藏刷新。当控制信号被断言预定的持续时间时，动态数据以第二刷新率刷新。在动态存储器单元阵列的隐藏刷新期间，隐藏刷新控制器耦合到动态存储器单元阵列。隐藏刷新控制器还被配置为监视识别来自存储器设备处的处理器的请求的控制信号，并且在控制信号被断言时以第一刷新率刷新动态数据。所述隐藏刷新控制器还被配置为当所述控制信号被断言预定持续时间时，以第二刷新率刷新所述动态数据。

20. 发明申请

US20060044913A1 Memory system and method using ECC to achieve low power refresh 有权
标题翻译：使用ECC实现低功耗刷新的内存系统和方法
公开(公告)号：US20060044913A1
公开(公告)日：2006-03-02
申请号：US11192971
申请日：2005-07-28
申请人： Dean Klein , John Schreck
发明人： Dean Klein , John Schreck
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G06F11/106 , G11C2211/4062
摘要： Rows of DRAM memory cells are refreshed at either a relatively high rate during normal operation or a relatively slow rate in a reduced power refresh mode. Prior to refreshing the rows of memory cells, the data are read from the memory cells, and corresponding syndromes are generated and stored. When transitioning from the reduced power refresh mode, data from the rows of memory cells are read, and the stored syndromes are used to determine if there are errors in the read data. The syndromes are also used to correct any errors that are found, and the corrected data are written to the rows of memory cells. By correcting any errors that exist when transitioning from the reduced power refresh mode, it is not necessary to use the syndromes to detect and correct errors while operating in the reduced power refresh mode.
摘要翻译： DRAM存储器单元的行在正常操作期间以相对高的速率刷新，或者在降低的功率刷新模式下刷新相对较慢的速率。在更新存储器单元的行之前，从存储器单元读取数据，并生成并存储相应的校正子。当从减小功率刷新模式转换时，读取来自存储器单元行的数据，并且使用所存储的校正子来确定读取数据中是否存在错误。综合征也用于校正发现的任何错误，并将校正的数据写入存储器单元的行。通过校正从减小功率刷新模式转换时存在的任何错误，在以降低功率刷新模式操作的情况下，不需要使用校正子来检测和校正错误。

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