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11. 发明授权

US07777212B2 Phase change memory devices including carbon-containing adhesive pattern 有权
标题翻译：相变存储器件包括含碳粘合剂图案
公开(公告)号：US07777212B2
公开(公告)日：2010-08-17
申请号：US11972198
申请日：2008-01-10
申请人： Hyeong-Geun An , Hideki Horii , Min-Young Park , Shin-Hye Kim
发明人： Hyeong-Geun An , Hideki Horii , Min-Young Park , Shin-Hye Kim
IPC分类号： H01L29/02
CPC分类号： H01L45/1658 , G11C13/0004 , G11C13/0069 , G11C2013/008 , G11C2213/35 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： Phase change memory devices include a heating electrode on a substrate and a phase change material pattern on the heating electrode. An adhesive pattern is disposed between the heating electrode and the phase change material pattern. The adhesive pattern contains carbon. Methods of fabricating phase change memory devices are also provided.
摘要翻译：相变存储器件包括衬底上的加热电极和加热电极上的相变材料图案。粘合剂图案设置在加热电极和相变材料图案之间。粘合剂图案含有碳。还提供了制造相变存储器件的方法。

12. 发明授权

US07638787B2 Phase changeable memory cell array region and method of forming the same 有权
标题翻译：相变存储单元阵列区域及其形成方法
公开(公告)号：US07638787B2
公开(公告)日：2009-12-29
申请号：US11581012
申请日：2006-10-16
申请人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
发明人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
IPC分类号： H01L29/02 , G11C11/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/165 , H01L45/1666
摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.
摘要翻译：相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。该区域还包括穿过下层间绝缘层设置的多个导电插塞。所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

13. 发明授权

US07563639B2 Phase-changeable memory device and method of manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07563639B2
公开(公告)日：2009-07-21
申请号：US11733131
申请日：2007-04-09
申请人： Hee-Ju Shin , Jong-Chan Shin , Soon-Oh Park , Hyeong-Geun An , Han-Bong Ko
发明人： Hee-Ju Shin , Jong-Chan Shin , Soon-Oh Park , Hyeong-Geun An , Han-Bong Ko
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： In a semiconductor memory device and a method of manufacturing the same, an insulating layer is formed on a substrate having a logic region on which a first pad is provided and a cell region on which a second pad and a lower electrode are subsequently provided. The insulating layer is etched to be a first insulating layer pattern having a first opening exposing the first pad. A first plug is formed in the first opening. The first insulating layer pattern where the first plug is formed is etched to be a second insulating layer pattern having a second opening exposing the lower electrode. A second plug including a phase-changeable material is formed in the second opening. A conductive wire and an upper electrode are formed on the first plug and the second plug, respectively.
摘要翻译：在半导体存储器件及其制造方法中，在具有设置有第一焊盘的逻辑区域的衬底上形成绝缘层，并且随后设置有第二焊盘和下电极的单元区域。绝缘层被蚀刻成具有第一开口的第一绝缘层图案，该第一开口露出第一焊盘。第一插头形成在第一开口中。将形成有第一插塞的第一绝缘层图案蚀刻成具有暴露下电极的第二开口的第二绝缘层图案。包括相变材料的第二插头形成在第二开口中。导线和上电极分别形成在第一插头和第二插头上。

14. 发明申请

US20060076548A1 PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same 有权
标题翻译：具有多个有序区域的垂直位置的PRAM及其形成方法
公开(公告)号：US20060076548A1
公开(公告)日：2006-04-13
申请号：US11246863
申请日：2005-10-07
申请人： Jae-Hyun Park , Hyeong-Geun An , Su-Jin Ahn , Yoon-Jong Song , Hyung-Joo Youn , Kyu-Chul Kim
发明人： Jae-Hyun Park , Hyeong-Geun An , Su-Jin Ahn , Yoon-Jong Song , Hyung-Joo Youn , Kyu-Chul Kim
IPC分类号： H01L29/02
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/144
摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.
摘要翻译：提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。其他半导体衬底分别限定其它有源区。在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。

15. 发明授权

US06717197B2 Ferroelectric memory device and method of fabricating the same 有权
标题翻译：铁电存储器件及其制造方法
公开(公告)号：US06717197B2
公开(公告)日：2004-04-06
申请号：US10245004
申请日：2002-09-16
申请人： Hyeong-Geun An
发明人： Hyeong-Geun An
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： A ferroelectric memory device and a method of fabricating the same are provided. The ferroelectric memory device includes at least two capacitor patterns and a plate line. Each of the capacitor patterns includes a lower electrode, a ferroelectric layer, and an upper electrode that are stacked on a semiconductor substrate. A top of the plate line is covered with an oxygen barrier layer, and a sidewall of the plate line is covered with an oxygen barrier spacer.
摘要翻译：提供了一种铁电存储器件及其制造方法。铁电存储器件包括至少两个电容器图案和板线。每个电容器图案包括堆叠在半导体衬底上的下电极，铁电层和上电极。板线的顶部被氧阻挡层覆盖，并且板状线的侧壁被氧隔离隔离物覆盖。

16. 发明授权

US08502184B2 Nonvolatile memory device using variable resistive element 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US08502184B2
公开(公告)日：2013-08-06
申请号：US13103013
申请日：2011-05-06
申请人： Hyeong-Geun An , Sung-Lae Cho , Ik-Soo Kim , Dong-Hyun Im , Eun-Hee Cho
发明人： Hyeong-Geun An , Sung-Lae Cho , Ik-Soo Kim , Dong-Hyun Im , Eun-Hee Cho
IPC分类号： H01L29/02
CPC分类号： H01L45/04 , H01L27/2427 , H01L27/249 , H01L45/1226
摘要： A nonvolatile memory device and a method of fabricating the same are provided. The nonvolatile memory device includes a conductive pillar that extends from a substrate in a first direction, a variable resistor that surrounds the conductive pillar, a switching material layer that surrounds the variable resistor, a first conductive layer that extends in a second direction, and a first electrode that extends in a third direction and contacts the first conductive layer and the switching material layer. Not one of the first, second, and third directions is parallel to another one of the first, second, and third directions.
摘要翻译：提供了一种非易失性存储器件及其制造方法。非易失性存储器件包括从第一方向从衬底延伸的导电柱，围绕导电柱的可变电阻器，围绕可变电阻器的开关材料层，沿第二方向延伸的第一导电层，以及第一电极，其在第三方向上延伸并接触第一导电层和开关材料层。第一，第二和第三方向中没有一个平行于第一，第二和第三方向的另一个。

17. 发明申请

US20110197812A1 APPARATUS AND METHOD FOR FABRICATING A PHASE-CHANGE MATERIAL LAYER 审中-公开
标题翻译：一种改变相变材料层的装置和方法
公开(公告)号：US20110197812A1
公开(公告)日：2011-08-18
申请号：US12965184
申请日：2010-12-10
申请人： Dong Hyun IM , Ik-Soo Kim , Sung-Lae Cho , Hyeong-Geun An
发明人： Dong Hyun IM , Ik-Soo Kim , Sung-Lae Cho , Hyeong-Geun An
IPC分类号： B05C11/10
CPC分类号： H01L45/1616 , C23C16/305 , C23C16/4481 , C23C16/4482 , C23C16/45553 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/144
摘要： Apparatus for fabricating a phase-change material layer include a process chamber. A first source supplier including a liquid delivery system (LDS) structure is coupled between a tellurium (Te) source container and the process chamber. A second source supplier including a bubbler method structure is coupled between at least one metal organic (MO) source container and the process chamber. Methods are also provided.
摘要翻译：用于制造相变材料层的装置包括处理室。包括液体输送系统（LDS）结构的第一源供应器耦合在碲（Te）源容器和处理室之间。包括起泡器方法结构的第二源供应器耦合在至少一个金属有机（MO）源容器和处理室之间。还提供了方法。

18. 发明申请

US20100055831A1 PHASE CHANGEABLE MEMORY CELL ARRAY REGION AND METHOD OF FORMING THE SAME 有权
标题翻译：相变记忆体区域及其形成方法
公开(公告)号：US20100055831A1
公开(公告)日：2010-03-04
申请号：US12617782
申请日：2009-11-13
申请人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
发明人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
IPC分类号： H01L21/06
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/165 , H01L45/1666
摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.
摘要翻译：相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。该区域还包括穿过下层间绝缘层设置的多个导电插塞。所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

19. 发明授权

US07638788B2 Phase change memory device and method of forming the same 有权
标题翻译：相变存储器件及其形成方法
公开(公告)号：US07638788B2
公开(公告)日：2009-12-29
申请号：US11974774
申请日：2007-10-16
申请人： Dong-Ho Ahn , Hideki Horii , Jong-Chan Shin , Jun-Soo Bae , Hyeong-Geun An
发明人： Dong-Ho Ahn , Hideki Horii , Jong-Chan Shin , Jun-Soo Bae , Hyeong-Geun An
IPC分类号： H01L29/04
CPC分类号： H01L45/143 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1226 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： Provided are a phase change memory device and a method of forming the same. According to the phase change memory, a first plug electrode and a second plug electrode are spaced apart from each other in a mold insulating layer. A phase change pattern is disposed on the mold insulating layer. The phase change pattern contacts a top of the first plug electrode and a first potion of a top of the second plug electrode. An interconnection is electrically connected to a second portion of the top of the second plug electrode.
摘要翻译：提供了一种相变存储器件及其形成方法。根据相变存储器，第一插头电极和第二插头电极在模具绝缘层中彼此间隔开。相变图案设置在模具绝缘层上。相变图案接触第一插头电极的顶部和第二插头电极的顶部的第一部分。互连电连接到第二插头电极的顶部的第二部分。

20. 发明授权

US07479405B2 PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same 有权
标题翻译： PRAMS具有顺序地定位的多个活性区域和形成该活性区域的方法
公开(公告)号：US07479405B2
公开(公告)日：2009-01-20
申请号：US11982940
申请日：2007-11-06
申请人： Jae-hyun Park , Hyeong-geun An , Su-jin Ahn , Yoon-jong Song , Hyung-joo Youn , Kyu-chul Kim
发明人： Jae-hyun Park , Hyeong-geun An , Su-jin Ahn , Yoon-jong Song , Hyung-joo Youn , Kyu-chul Kim
IPC分类号： H01L21/00
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/144
摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.
摘要翻译：提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。其他半导体衬底分别限定其它有源区。在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。

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