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11. 发明授权

US06907487B2 Enhanced highly pipelined bus architecture 失效
标题翻译：增强高流水线总线架构
公开(公告)号：US06907487B2
公开(公告)日：2005-06-14
申请号：US09783852
申请日：2001-02-14
申请人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
发明人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
IPC分类号： G06F13/36 , G06F13/42 , G06F13/14
CPC分类号： G06F13/4217
摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to drive data elements at four times the clock frequency. The address bus interface drives a substantially centered address strobe transition for each address element, and the data bus interface drives a substantially centered data strobe transition for each data element.
摘要翻译：可用于增强的高流水线总线架构中的总线代理。在一个实施例中，总线代理包括用于以时钟频率驱动控制信号的控制接口，用于以两倍时钟频率驱动地址元件的地址总线接口和用于以四倍于时钟频率驱动数据元素的数据总线接口。地址总线接口为每个地址元件驱动基本中心的地址选通转换，并且数据总线接口为每个数据元件驱动基本中心的数据选通转换。

12. 发明授权

US06806583B2 Light source 有权
标题翻译：光源
公开(公告)号：US06806583B2
公开(公告)日：2004-10-19
申请号：US09888857
申请日：2001-06-25
申请人： Huck Khim Koay , Seong Choon Lim , Cheng Why Tan , Gurbir Singh A/L Balwant Singh , Chee Keong Chong , Sundar a/l Natarajan Yoganandan
发明人： Huck Khim Koay , Seong Choon Lim , Cheng Why Tan , Gurbir Singh A/L Balwant Singh , Chee Keong Chong , Sundar a/l Natarajan Yoganandan
IPC分类号： H01L2328
CPC分类号： H01L33/486 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/92247 , H01L2924/10253 , H01L2924/00014 , H01L2924/00
摘要： A light source suitable for surface mounting onto a printed circuit board. The light source includes a planar substrate with a centrally positioned recess. A light emitting diode is mounted in the recess and the substrate is encapsulated by a transparent encapsulant material forming an ellipsoidal dome over the light emitting diode.
摘要翻译：适用于表面安装到印刷电路板上的光源。光源包括具有中心定位的凹部的平面基板。发光二极管安装在凹槽中，并且衬底被透明的密封剂材料封装，该透明密封材料在发光二极管上形成椭圆形的圆顶。

13. 再颁专利

USRE38388E1 Method and apparatus for performing deferred transactions 有权
标题翻译：执行延期交易的方法和装置
公开(公告)号：USRE38388E1
公开(公告)日：2004-01-13
申请号：US09882444
申请日：2001-06-14
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
IPC分类号： H04L12417
CPC分类号： G06F13/368 , G06F13/4213
摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

14. 发明授权

US5923857A Method and apparatus for ordering writeback data transfers on a bus 失效
标题翻译：在总线上订购回写数据传输的方法和装置
公开(公告)号：US5923857A
公开(公告)日：1999-07-13
申请号：US708922
申请日：1996-09-06
申请人： Stephen S. Pawlowski , Peter D. MacWilliams , Nitin V. Sarangdhar , Gurbir Singh
发明人： Stephen S. Pawlowski , Peter D. MacWilliams , Nitin V. Sarangdhar , Gurbir Singh
IPC分类号： G06F12/08 , G06F13/14 , G06F12/00
CPC分类号： G06F12/0831
摘要： A method and apparatus for ordering data transfers includes an identifier of a critical portion of data being received from a requesting agent along with a request for data. Writeback data corresponding to the requested data is then transferred to the bus as a plurality of portions and ordered to ensure that a first portion which includes the critical portion of the data is transferred to the bus first.
摘要翻译：用于排序数据传输的方法和装置包括从请求代理接收的数据的关键部分的标识符以及数据请求。然后将与所请求的数据相对应的回写数据作为多个部分传送到总线，并被排序以确保包括数据的关键部分的第一部分首先被传送到总线。

15. 发明授权

US5911053A Method and apparatus for changing data transfer widths in a computer system 失效
标题翻译：用于在计算机系统中改变数据传输宽度的方法和装置
公开(公告)号：US5911053A
公开(公告)日：1999-06-08
申请号：US723572
申请日：1996-09-30
申请人： Stephen S. Pawlowski , Peter D. MacWilliams , Gurbir Singh
发明人： Stephen S. Pawlowski , Peter D. MacWilliams , Gurbir Singh
IPC分类号： G06F13/40 , G06F3/00
CPC分类号： G06F13/4018
摘要： In a method and apparatus for changing data transfer widths in a computer system, a first agent on a bus provides a first indication to a second agent on the bus identifying one or more data transfer widths supported by the first agent. The second agent then provides a second indication to the first agent identifying one or more data transfer widths supported by the second agent. A data transfer width is then determined based on the first indication and the second indication. According to an embodiment of the present invention, a third agent involved in a transaction is also able to provide a third indication to the first and/or second agents identifying one or more data transfer widths supported by the third agent. The data transfer width(s) is then determined based on the first, second, and third indications.
摘要翻译：在用于改变计算机系统中的数据传输宽度的方法和装置中，总线上的第一代理向总线上的第二代理提供第一指示，以识别第一代理所支持的一个或多个数据传输宽度。然后，第二代理向第一代理提供识别由第二代理支持的一个或多个数据传输宽度的第二指示。然后基于第一指示和第二指示确定数据传输宽度。根据本发明的实施例，参与交易的第三代理还能够向第一代理和/或第二代理提供第三指示，以识别由第三代理支持的一个或多个数据传输宽度。然后基于第一，第二和第三指示确定数据传送宽度。

16. 发明授权

US5809524A Method and apparatus for cache memory replacement line identification 失效
标题翻译：用于高速缓存存储器替换线路识别的方法和装置
公开(公告)号：US5809524A
公开(公告)日：1998-09-15
申请号：US822044
申请日：1997-03-24
申请人： Gurbir Singh , Wen-Hann Wang , Michael W. Rhodehamel , John M. Bauer , Nitin V. Sarangdhar
发明人： Gurbir Singh , Wen-Hann Wang , Michael W. Rhodehamel , John M. Bauer , Nitin V. Sarangdhar
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/123 , G06F12/0831
摘要： A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers requested addresses from the controller to the cache memory. The data bus transfers data associated with requested addresses from the controller to the cache memory, and also transfers replacement line addresses from the cache memory to the controller. The status bus transfers status information associated with the requested addresses from the cache memory to the controller which indicate whether the requested addresses are contained in the cache memory. In one embodiment, the data bus also transfers cache line data associated with a requested address from the cache memory to the controller when the requested address hits the cache memory.
摘要翻译：一种用于高速缓存存储器替代线路识别的方法和装置具有缓存接口，其提供高速缓冲存储器和用于高速缓冲存储器的控制器之间的通信接口。该接口包括地址总线，数据总线和状态总线。地址总线将请求的地址从控制器传送到高速缓冲存储器。数据总线将与请求的地址相关联的数据从控制器传送到高速缓冲存储器，并且还将替换行地址从高速缓冲存储器传送到控制器。状态总线将与请求的地址相关联的状态信息从高速缓冲存储器传送到控制器，该控制器指示所请求的地址是否包含在高速缓冲存储器中。在一个实施例中，当请求的地址与高速缓冲存储器匹配时，数据总线还将与所请求的地址相关联的高速缓存行数据从高速缓冲存储器传送到控制器。

17. 发明授权

US5796977A Highly pipelined bus architecture 失效
标题翻译：高度流水线总线架构
公开(公告)号：US5796977A
公开(公告)日：1998-08-18
申请号：US688238
申请日：1996-07-29
申请人： Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
IPC分类号： G06F12/08 , G06F13/18 , G06F12/00 , G06F13/00
CPC分类号： G06F13/18 , G06F12/0831
摘要： A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.
摘要翻译：描述了包含维护数据一致性的流水线总线的计算机系统，支持长延迟事务并提供处理器顺序。计算机系统包括总线代理，其具有在系统总线上跟踪多个未完成事务的按顺序队列，并且响应于在一个事务中提供窥探结果和修改的数据的事务请求来执行窥探。此外，系统通过在用于重新启动延迟事务的事务请求期间提供延迟标识符来支持长延迟事务。

18. 发明授权

US5754833A Method and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a P/Q integer ratio 失效
标题翻译：用于在具有P / Q整数比的频率下操作的数字设备之间提供同步数据传输的方法和装置
公开(公告)号：US5754833A
公开(公告)日：1998-05-19
申请号：US788356
申请日：1997-01-24
申请人： Gurbir Singh , Michael W. Rhodehamel
发明人： Gurbir Singh , Michael W. Rhodehamel
IPC分类号： G06F13/42 , G06F1/12 , G06F13/40 , H03K5/135 , H03K5/153 , H03K5/26 , H03L7/183 , H04L7/00
CPC分类号： H03K5/26 , G06F13/405 , H03K5/135 , H03K5/153 , H03L7/183 , H04L7/0012
摘要： An apparatus for synchronously transmitting data between devices operating at different frequencies that have a P/Q integer ratio relationship. The apparatus allows one or more device(s) operating at a high frequency to synchronously exchange data with one or more device(s) operating at a low frequency. The low and high frequencies have a P/Q integer ratio relationship of: low frequency=(P/Q).times.high frequency; where P and Q represent integer values, P is less than Q, and Q is not necessarily an integer multiple of P. A P/Q clock generator generates one or both of the high and low frequency clocks according to the P/Q frequency ratio. An interface controller receives the high frequency clock and the P and Q values as inputs and generates a high-to-low data transfer signal for enabling data transfers from high frequency to low frequency devices. The interface controller also generates a low-to-high frequency data transfer signal for enabling data transfers from low to high frequency devices. The data transfer signals may be used to latch or qualify transfer data during transfer across frequency boundaries. The data transfer signals indicate safe times, or windows, for transferring data across frequency boundaries. A safe time for transferring data across a frequency boundary is a high frequency clock period where the transfer data is stable and the receiving device can receive the data.
摘要翻译：一种在具有P / Q整数比关系的不同频率工作的设备之间同步发送数据的装置。该装置允许以高频率操作的一个或多个设备与以低频操作的一个或多个设备同步地交换数据。低频和高频具有P / Q整数比关系：低频=（P / Q）×高频; 其中P和Q表示整数值，P小于Q，Q不一定是P的整数倍.P / Q时钟发生器根据P / Q频率比产生高频和低频时钟中的一个或两个。接口控制器接收高频时钟和P和Q值作为输入，并产生高到低的数据传输信号，用于实现从高频到低频器件的数据传输。接口控制器还产生低到高频数据传输信号，用于实现从低频到高频器件的数据传输。数据传输信号可用于在跨频率边界传输期间锁存或限定传输数据。数据传输信号表示跨越频率边界传输数据的安全时间或窗口。跨频率传输数据的安全时间是传输数据稳定且接收设备可以接收数据的高频时钟周期。

19. 发明授权

US07937418B2 Method and system for enhancing software documentation and help systems 有权
标题翻译：用于增强软件文档和帮助系统的方法和系统
公开(公告)号：US07937418B2
公开(公告)日：2011-05-03
申请号：US12345621
申请日：2008-12-29
申请人： Gurbir Singh
发明人： Gurbir Singh
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： G06F8/73 , G06F9/453
摘要： A method and system for enhancing software documentation and help systems. In one embodiment, a virtual library for a selected combination of tools is created. The virtual library is then linked to the tools in the selected combination of tools. In another embodiment, a combination of tools for designing a complex software system is selected from one or more software releases. The one or more software releases comprises a plurality of available tools. The selected combination of tools comprises less than all of the plurality of available tools. Each of the plurality of available tools is associated with one or more documents. Access to only those one or more documents associated with tools in the selected combination of tools is provided.
摘要翻译：一种用于增强软件文档和帮助系统的方法和系统。在一个实施例中，创建用于所选择的工具组合的虚拟库。然后将虚拟库链接到所选择的工具组合中的工具。在另一个实施例中，从一个或多个软件版本中选择用于设计复杂软件系统的工具的组合。一个或多个软件版本包括多个可用的工具。所选择的工具组合包括少于所有多个可用工具。多个可用工具中的每一个与一个或多个文档相关联。提供了仅选择与所选择的工具组合中的工具相关联的那些一个或多个文档。

20. 发明授权

US07112916B2 Light emitting diode based light source emitting collimated light 有权
标题翻译：基于发光二极管的光源发射准直光
公开(公告)号：US07112916B2
公开(公告)日：2006-09-26
申请号：US10267759
申请日：2002-10-09
申请人： Kee Siang Goh , Boon Kheng Lee , Yee Loong Chin , Gurbir Singh
发明人： Kee Siang Goh , Boon Kheng Lee , Yee Loong Chin , Gurbir Singh
IPC分类号： H05B33/04
CPC分类号： H01L33/60 , H01L33/44 , H01L33/46 , Y10S362/80
摘要： A light emitting diode, a reflector and a platform are employed within a light source. The light emitting diode emits light exclusively from its side surfaces. The reflector has a parabolic reflective surface that collimates any portion of the light reflecting from the parabolic reflective surface. The platform supports a centering of the light emitting layer(s) of the light emitting diode on a focus point of the parabolic reflective surface.
摘要翻译：在光源内采用发光二极管，反射器和平台。发光二极管从其侧表面专门发光。反射器具有抛物面反射表面，其对来自抛物面反射表面的光的任何部分进行准直。平台支持在抛物面反射表面的焦点上的发光二极管的发光层的定心。

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