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11. 发明申请

US20060125542A1 Point diffusion signal distribution with minimized power consumption and signal skew 有权
标题翻译：点扩散信号分布，功耗和信号偏移最小化
公开(公告)号：US20060125542A1
公开(公告)日：2006-06-15
申请号：US11297004
申请日：2005-12-08
申请人： Gun-Ok Jung , Young-Min Shin
发明人： Gun-Ok Jung , Young-Min Shin
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： For distributing a signal to loads in an area, the area is divided into a plurality of regions. A respective signal point is disposed in each region for providing the signal to a load in the region. A respective diffusion point is disposed between any two neighboring signal points. The signal is initially applied to a center point of the signal and diffusion points. The signal when received at a given signal or diffusion point is transmitted to any of the signal or diffusion points within a maximum distance from the given signal or diffusion point.
摘要翻译：为了将信号分配到区域中的负载，该区域被分成多个区域。相应的信号点设置在每个区域中，用于向该区域中的负载提供信号。相应的扩散点设置在任何两个相邻信号点之间。信号最初被施加到信号和扩散点的中心点。在给定信号或扩散点处接收到的信号被传送到与给定信号或扩散点的最大距离内的任何信号或扩散点。

12. 发明申请

US20120223739A1 FLIP-FLOP AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：包括其的FLIP-FLOP和SEMICONDUCTOR DEVICE
公开(公告)号：US20120223739A1
公开(公告)日：2012-09-06
申请号：US13410468
申请日：2012-03-02
申请人： Gun Ok JUNG , Min Su Kim , Uk Rae Cho , Dae Young Moon , Hyoung Wook Lee
发明人： Gun Ok JUNG , Min Su Kim , Uk Rae Cho , Dae Young Moon , Hyoung Wook Lee
IPC分类号： H03K19/173
CPC分类号： G01R31/318541 , H03K3/356121
摘要： A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals.
摘要翻译：提供了一个触发器。触发器包括第一锁存电路，其被配置为响应于多个第一控制信号锁存数据信号或响应于多个第二控制信号锁存扫描输入信号，以及第二锁存电路，被配置为锁存信号响应于互补的时钟信号从第一锁存电路输出。

13. 发明申请

US20120139584A1 DOMINO LOGIC CIRCUITS AND PIPELINED DOMINO LOGIC CIRCUITS 有权
标题翻译：多米尼加逻辑电路和管道多米诺逻辑电路
公开(公告)号：US20120139584A1
公开(公告)日：2012-06-07
申请号：US13234811
申请日：2011-09-16
申请人： Hyoung-Wook Lee , Gun-Ok Jung , Suhwan Kim , Ah-Reum Kim , Rahul Singh
发明人： Hyoung-Wook Lee , Gun-Ok Jung , Suhwan Kim , Ah-Reum Kim , Rahul Singh
IPC分类号： H03K19/096
CPC分类号： H03K19/0966
摘要： A domino logic circuit includes a first evaluation unit, a second evaluation unit and an output unit. The first evaluation unit precharges a first dynamic node, discharges a footer node in a first phase of a clock signal, and evaluates a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal. The second evaluation unit precharges a second dynamic node in the first phase of the clock signal, and determines a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal. The output unit provides an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node.
摘要翻译：多米诺逻辑电路包括第一评估单元，第二评估单元和输出单元。第一评估单元对第一动态节点进行预充电，在时钟信号的第一阶段放电页脚节点，并且评估多个输入信号以在时钟信号的第二阶段中确定第一动态节点的逻辑电平。第二评估单元在时钟信号的第一阶段中对第二动态节点进行预充电，并且响应于时钟信号的第二阶段中的页脚节点的逻辑电平来确定第二动态节点的逻辑电平。输出单元提供具有根据第一动态节点的第一电压的电平和第二动态节点的第二电压的逻辑电平的输出信号。

14. 发明授权

US07705656B2 Leakage current detection circuit and leakage current comparison circuit 有权
标题翻译：泄漏电流检测电路和漏电流比较电路
公开(公告)号：US07705656B2
公开(公告)日：2010-04-27
申请号：US11481275
申请日：2006-07-05
申请人： Gun-Ok Jung
发明人： Gun-Ok Jung
IPC分类号： H03K17/687
CPC分类号： G01R31/275 , G01R31/2621 , G01R31/3008 , H03K2217/0036
摘要： A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.
摘要翻译：泄漏电流测量电路，其响应于MOS晶体管和泄漏电流比较电路的尺寸变化来测量衬底漏电流和栅极漏电流，判断衬底泄漏电流和栅极漏电流中的哪一个占优势。泄漏电流测量电路包括电荷源，漏电流发生器和检测信号发生器。泄漏电流比较电路包括电荷源，漏电流比较器和检测信号发生器。

15. 发明申请

US20070025030A1 Leakage current detection circuit and leakage current comparison circuit 有权
标题翻译：泄漏电流检测电路和漏电流比较电路
公开(公告)号：US20070025030A1
公开(公告)日：2007-02-01
申请号：US11481275
申请日：2006-07-05
申请人： Gun-Ok Jung
发明人： Gun-Ok Jung
IPC分类号： H02H7/00
CPC分类号： G01R31/275 , G01R31/2621 , G01R31/3008 , H03K2217/0036
摘要： A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.
摘要翻译：泄漏电流测量电路，其响应于MOS晶体管和泄漏电流比较电路的尺寸变化来测量衬底漏电流和栅极漏电流，判断衬底泄漏电流和栅极漏电流中的哪一个占优势。泄漏电流测量电路包括电荷源，漏电流发生器和检测信号发生器。泄漏电流比较电路包括充电电源，漏电流比较器和检测信号发生器。

16. 发明授权

US07106117B2 Delayed clock signal generator 有权
标题翻译：延时时钟信号发生器
公开(公告)号：US07106117B2
公开(公告)日：2006-09-12
申请号：US10910644
申请日：2004-08-04
申请人： Gun-Ok Jung , Jin-Han Kim , Sung-Bae Park , Chul-Woo Kim , Seok-Soo Yoon , Seok-Ryoung Yoon
发明人： Gun-Ok Jung , Jin-Han Kim , Sung-Bae Park , Chul-Woo Kim , Seok-Soo Yoon , Seok-Ryoung Yoon
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K5/135 , H03K2005/00156 , H03K2005/00286
摘要： A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a phase detect circuit for generating a selecting signal based on the amount of phase delay detected according to a half-cycle (π), and in comparison with the clock signal, a phase interpolation circuit for controlling the delay time of the delayed clock signals and interpolating the delayed clock signals, and a selecting circuit which outputs the delayed clock signal delayed by a specified phase difference.
摘要翻译：一种可被配置为通过指定的相位差产生延迟的时钟信号的装置，其可以包括用于产生至少一个时钟信号的时钟发生器电路，用于延迟所述至少一个时钟信号的延迟时钟信号发生器，相位检测电路用于基于根据半周期（pi）检测到的相位延迟量来生成选择信号，并且与时钟信号相比，相位插值电路用于控制延迟的时钟信号的延迟时间并内插延迟的时钟信号，以及输出延迟了指定相位差的延迟时钟信号的选择电路。

17. 发明授权

US09158354B2 Footer-less NP domino logic circuit and related apparatus 有权
标题翻译：无脚踏NP多米诺逻辑电路及相关设备
公开(公告)号：US09158354B2
公开(公告)日：2015-10-13
申请号：US13795852
申请日：2013-03-12
申请人： Ken Keon Shin , Hoi Jin Lee , Gun Ok Jung , Min Su Kim
发明人： Ken Keon Shin , Hoi Jin Lee , Gun Ok Jung , Min Su Kim
IPC分类号： G06F1/04 , G06F1/32 , H03K19/00 , H03K19/096
CPC分类号： G06F1/32 , G06F1/04 , H03K19/0008 , H03K19/0963
摘要： A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node.
摘要翻译：多米诺骨牌逻辑电路包括响应于时钟信号对第一动态节点预充电的预充电电路，第一逻辑网络响应于第一数据信号确定第一动态节点的逻辑电平，反相器接收时钟信号响应于逆变器的输出信号而放电第二动态节点的放电电路，以及响应于至少一个第二数据信号和第一动态节点的输出信号确定第二动态节点的逻辑电平的第二逻辑网络节点。

18. 发明授权

US08531208B2 Flip-flop and semiconductor device including the same 有权
标题翻译：触发器和包括其的半导体器件
公开(公告)号：US08531208B2
公开(公告)日：2013-09-10
申请号：US13410468
申请日：2012-03-02
申请人： Gun Ok Jung , Min Su Kim , Uk Rae Cho , Dae Young Moon , Hyoung Wook Lee
发明人： Gun Ok Jung , Min Su Kim , Uk Rae Cho , Dae Young Moon , Hyoung Wook Lee
IPC分类号： H03K19/173
CPC分类号： G01R31/318541 , H03K3/356121
摘要： A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals.
摘要翻译：提供了一个触发器。触发器包括第一锁存电路，其被配置为响应于多个第一控制信号锁存数据信号或响应于多个第二控制信号锁存扫描输入信号，以及第二锁存电路，被配置为锁存信号响应于互补的时钟信号从第一锁存电路输出。

19. 发明申请

US20130194019A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATING DEVICE INCLUDING THE SAME 审中-公开
标题翻译：半导体集成电路及其操作装置的方法
公开(公告)号：US20130194019A1
公开(公告)日：2013-08-01
申请号：US13613953
申请日：2012-09-13
申请人： Hoi Jin Lee , Gun Ok Jung
发明人： Hoi Jin Lee , Gun Ok Jung
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , H03K3/356156
摘要： The semiconductor integrated circuit includes a clock tree that transmits a clock signal to a plurality of tree branches, a plurality of pulse generators, and a plurality of pulse distribution networks. Each pulse generator generates a pulse in response to the clock signal transmitted through the tree branches. Each pulse distribution network is in communication with a pulse generator of the plurality of pulse generators, and is constructed and arranged to transmit the pulse generated by each pulse generator to a plurality of pulse sinks.
摘要翻译：半导体集成电路包括将时钟信号发送到多个树枝，多个脉冲发生器和多个脉冲分配网络的时钟树。每个脉冲发生器响应于通过树枝传输的时钟信号产生脉冲。每个脉冲分配网络与多个脉冲发生器中的脉冲发生器通信，并且被构造和布置成将由每个脉冲发生器产生的脉冲发送到多个脉冲发生器。

20. 发明授权

US07893718B2 High-speed multiplexer and semiconductor device including the same 有权
标题翻译：高速多路复用器和包括相同的半导体器件
公开(公告)号：US07893718B2
公开(公告)日：2011-02-22
申请号：US12540465
申请日：2009-08-13
申请人： Sung Bae Park , Gun Ok Jung , Young Min Shin , Hoi Jin Lee , Chang Jun Choi , Min Su Kim
发明人： Sung Bae Park , Gun Ok Jung , Young Min Shin , Hoi Jin Lee , Chang Jun Choi , Min Su Kim
IPC分类号： H03K19/094
CPC分类号： H03K19/1737 , H03K17/005 , H03K17/693 , H03K19/0013 , H03K2217/0036
摘要： High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit.
摘要翻译：高速多路复用器包括第一N-1选择电路，其中N是大于1的整数，第二N-1选择电路和输出驱动器。第一N-1选择电路被配置为响应于第一多位选择信号将所选择的第一输入信号（从N个输入信号中）的真或互补版本路由到其输出，其中N是大于1的整数。第二N-1选择电路被配置为响应于第二多位选择信号将所选择的第一输入信号的真实或互补版本路由到其输出。输出驱动器包括上拉电路，其响应于在第一N-1选择电路的输出处产生的信号，以及下拉电路，其响应于在输出端产生的信号第二个N到1选择电路。

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