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11. 发明申请

US20100276607A1 Method of depositing protective structures 有权
标题翻译：沉积保护结构的方法
公开(公告)号：US20100276607A1
公开(公告)日：2010-11-04
申请号：US12658507
申请日：2010-02-05
申请人： Heinz Wanzenboeck , Wolfram Buehler , Holger Doemer , Carl Kuebler , Daniel Fischer , Gottfried Hochleitner , Emmerich Bertagnolli
发明人： Heinz Wanzenboeck , Wolfram Buehler , Holger Doemer , Carl Kuebler , Daniel Fischer , Gottfried Hochleitner , Emmerich Bertagnolli
IPC分类号： G21K5/08 , C23C16/06 , C23C16/02 , C23C16/48
CPC分类号： G01N1/28 , G01N1/286 , H01J37/26 , H01J37/261 , H01J37/3056 , H01J2237/31745 , H01J2237/31749
摘要： A process of preparing a lamella from a substrate includes manufacturing a protection strip on an edge portion of the lamella to be prepared from the substrate, and preparing the lamella, wherein the manufacturing the protection strip includes a first phase of activating a surface area portion of the substrate, and a second phase of electron beam assisted deposition of the protective strip on the activated surface area portion from the gas phase.
摘要翻译：从衬底制备薄片的方法包括在待从衬底制备的薄片的边缘部分上制造保护条，并制备薄片，其中制造保护条包括激活第一阶段的第一阶段衬底以及电子束辅助沉积在气相的活化表面积部分上的保护带的第二相。

12. 发明授权

US07084442B2 Double gate transistor arrangement for receiving electrical signals from living cells 失效
标题翻译：用于从活细胞接收电信号的双栅晶体管布置
公开(公告)号：US07084442B2
公开(公告)日：2006-08-01
申请号：US10922545
申请日：2004-08-19
申请人： Emmerich Bertagnolli
发明人： Emmerich Bertagnolli
IPC分类号： H01L23/58
CPC分类号： A61N1/36 , G01N27/414 , G01N33/48728 , H01L2924/0002 , H01L2924/00
摘要： The invention involves an array to couple a live cell, in particular a nerve cell, with an electronic circuit to pick up directly or indirectly electrically active cell signals and/or to electronically stimulate the cell, where the coupling array comprises a transistor (T1) with a double gate, where one of the gates is designed as a control gate (CG) to select the transistor via external control signals, and the other gate (FG) is connected to an electrically conducting contact element (1) which may be brought into contact with the cell (2) to register changes in the electric properties of the cell.
摘要翻译：本发明涉及一种将活细胞，特别是神经细胞与电子电路耦合以将电活动的细胞信号直接或间接地吸收和/或电子刺激细胞的阵列，其中耦合阵列包括晶体管（T 1 ），其中一个栅极被设计为通过外部控制信号选择晶体管的控制栅极（CG），而另一个栅极（FG）连接到导电接触元件（1），导电接触元件与电池（2）接触以记录电池电性能的变化。

13. 发明授权

US06566202B2 Integrated circuit having at least two vertical MOS transistors and method for manufacturing same 有权
公开(公告)号：US06566202B2
公开(公告)日：2003-05-20
申请号：US10081902
申请日：2002-02-22
申请人： Bernd Goebel , Emmerich Bertagnolli
发明人： Bernd Goebel , Emmerich Bertagnolli
IPC分类号： H01L2100
CPC分类号： H01L21/823885 , H01L27/092
摘要： An integrated circuit having at least two vertical MOS transistors, and method for manufacturing same, wherein first source/drain regions of the two vertical MOS transistors are located in an upper region of sidewalls of a trench. A second source/drain region is shared by both MOS transistors and is adjacent at a floor of the trench. Gate electrodes of the MOS transistors that are arranged at the sidewalls of the trench can be individually contacted via parts of a conductive layer that are arranged above the first source/drain regions. In a manufacturing method, such arrangement is made possible by the deposition of a conductive layer of doped polysilicon before the generation of the trench. The area of an MOS transistor can amount to 4F2.

14. 发明授权

US6097049A DRAM cell arrangement 有权
标题翻译： DRAM单元布置
公开(公告)号：US6097049A
公开(公告)日：2000-08-01
申请号：US272077
申请日：1999-03-18
申请人： Bernd Goebel , Eve Marie Martin , Emmerich Bertagnolli
发明人： Bernd Goebel , Eve Marie Martin , Emmerich Bertagnolli
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10852 , H01L27/10823 , H01L27/10876 , Y10S257/906 , Y10S257/907
摘要： A DRAM cell arrangement and method for manufacturing same, wherein a storage capacitor is connected via a first source/drain zone of a vertical selection transistor and a bit line. Since the storage capacitor and the bit line are arranged substantially above a substrate, the bit line can be manufactured of materials having high electrical conductivity, and materials having a high dielectric constant can be utilized for the storage capacitor. At least the first source/drain zone and a channel zone are parts of a projection-like semiconductor structure that is laterally limited by at least two sidewalls. A respective word line can be arranged at the two sidewalls. An element that prevents the drive of the selection transistor by this word line is arranged between the channel zone and one of the word lines. A second source/drain zone of the selection transistor is buried in the substrate and, for example, is part of a doped layer or of a grid-shaped doped region or is connected to the substrate via a buried contact. A memory cell can be manufactured given open bit lines as well as given folded bit lines, wherein it is manufactured with an area of 4F.sup.2.
摘要翻译：一种DRAM单元布置及其制造方法，其中存储电容器经由垂直选择晶体管的第一源极/漏极区域和位线连接。由于存储电容器和位线布置在基板的大致上方，所以位线可以由具有高导电性的材料制造，并且具有高介电常数的材料可用于存储电容器。至少第一源极/漏极区域和沟道区域是由至少两个侧壁横向限制的突起状半导体结构的部分。相应的字线可以布置在两个侧壁处。阻止由该字线驱动选择晶体管的元件被布置在通道区域和一条字线之间。选择晶体管的第二源极/漏极区域被掩埋在衬底中，并且例如是掺杂层或栅格形掺杂区域的一部分，或者通过埋入触点连接到衬底。可以制造给定的开放位线以及给定的折叠位线的存储器单元，其中制造的面积为4F2。

15. 发明授权

US6075265A DRAM cell arrangement and method for its fabrication 失效
标题翻译： DRAM单元布置及其制造方法
公开(公告)号：US6075265A
公开(公告)日：2000-06-13
申请号：US105235
申请日：1998-06-26
申请人： Bernd Goebel , Emmerich Bertagnolli
发明人： Bernd Goebel , Emmerich Bertagnolli
IPC分类号： G11C11/34 , G11C11/405 , H01L21/82 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/108 , H01L27/10876 , H01L27/10852
摘要： The DRAM cell arrangement has three transistors per memory cell, at least one of which transistors is designed as a vertical transistor. The transistors may be formed on sidewalls (1F1, 1F2, 2F2) of trenches (G1, G2). In order to fabricate contact regions (K) which respectively connect together three source/drain regions (1 S/D1, 3 S/D2, 2 S/D 2) of different transistors, it is advantageous to arrange the trenches (G1, G2) alternately with a larger distance and a smaller distance from one another. Gate electrodes (Ga1, Ga3) of transistors may be formed as parts of writing word lines (WS) or read-out word lines (WA) in the form of spacers on sidewalls (1F1, 1F2) of the trenches (G1). Connections between gate electrodes (Ga2) and source/drain regions (3 S/D1) may be made via conductive structures (L).
摘要翻译：每个存储单元DRAM单元布置具有三个晶体管，其中至少一个晶体管被设计为垂直晶体管。晶体管可以形成在沟槽（G1，G2）的侧壁（1F1,1F2,2F2）上。为了制造分别连接不同晶体管的三个源极/漏极区域（1S / D1,3S / D2,2S / D 2）的接触区域（K），有利的是将沟槽（G1，G2））交替地具有较大的距离和彼此较小的距离。晶体管的栅电极（Ga1，Ga3）可以形成为在沟槽（G1）的侧壁（1F1,1F2）上的间隔物形式的写入字线（WS）或读出字线（WA）的部分。栅电极（Ga2）和源/漏区（3S / D1）之间的连接可以通过导电结构（L）制成。

16. 发明授权

US5358882A Method for manufacturing a bipolar transistor in a substrate 失效
标题翻译：在基板中制造双极晶体管的方法
公开(公告)号：US5358882A
公开(公告)日：1994-10-25
申请号：US030901
申请日：1993-03-15
申请人： Emmerich Bertagnolli , Helmut Klose
发明人： Emmerich Bertagnolli , Helmut Klose
IPC分类号： H01L29/73 , H01L21/331 , H01L21/74 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66272 , H01L21/743 , H01L29/7325 , Y10S148/011
摘要： A method for producing a bipolar transistor completely surrounded by an insulating trench in a substrate. Insulating regions at the surface of the substrate can be produced by depositing an SiO.sub.2 layer on the basis of thermal decomposition of TEOS and subsequent structuring of the SiO.sub.2 layer. The insulating regions can be employed as a self-aligning mask for the production of a collector terminal and of a substrate terminal.
摘要翻译：一种完全由基板中的绝缘沟槽围绕的双极晶体管的制造方法。可以通过在TEOS的热分解和SiO 2层的结构化的基础上沉积SiO 2层来制造衬底表面的绝缘区域。绝缘区域可以用作用于生产集电极端子和衬底端子的自对准掩模。

17. 发明授权

US5213670A Method for manufacturing a polycrystalline layer on a substrate 失效
标题翻译：在基板上制造多晶层的方法
公开(公告)号：US5213670A
公开(公告)日：1993-05-25
申请号：US745957
申请日：1991-08-09
申请人： Emmerich Bertagnolli , Herbert Kabza
发明人： Emmerich Bertagnolli , Herbert Kabza
IPC分类号： C23C14/14 , C23C14/58 , C23C16/24 , C23C16/56 , H01L21/02 , H01L21/321
CPC分类号： C23C14/5806 , C23C14/14 , C23C14/58 , C23C14/584 , C23C16/24 , C23C16/56 , H01L21/321 , H01L28/20
摘要： A manufacturing method for polycrystalline silicon layers with a defined particle size and texture on a substrate provides for depositing of an amorphous silicon layer on the substrate. The substrate with the amorphous silicon layer is placed into a furnace at an initial temperature lower than the crystallization temperature of amorphous silicon. After an adjustment to thermal equilibrium, the furnace is heated in a controlled fashion from the initial temperature to a target temperature which is higher than the crystallization temperature, whereby the amorphous silicon layer is completely crystallized and becomes a polycrystalline layer. The method is particularly applicable in manufacturing polycrystalline silicon resistances for integrated circuits.
摘要翻译：在衬底上具有确定的粒度和纹理的多晶硅层的制造方法提供了在衬底上沉积非晶硅层。将具有非晶硅层的衬底置于比非晶硅的结晶温度低的初始温度下的炉中。在对热平衡进行调整之后，以从控制的方式将炉子从初始温度加热到高于结晶温度的目标温度，从而使非晶硅层完全结晶并变成多晶层。该方法特别适用于制造用于集成电路的多晶硅电阻。

18. 发明授权

US4889823A Bipolar transistor structure for very high speed circuits and method for the manufacture thereof 失效
标题翻译：用于非常高速电路的双极晶体管结构及其制造方法
公开(公告)号：US4889823A
公开(公告)日：1989-12-26
申请号：US358672
申请日：1989-05-30
申请人： Emmerich Bertagnolli , Peter Weger
发明人： Emmerich Bertagnolli , Peter Weger
IPC分类号： H01L29/73 , H01L21/225 , H01L21/285 , H01L21/331 , H01L21/8222 , H01L21/8229 , H01L27/06 , H01L27/082 , H01L27/102 , H01L29/08 , H01L29/417 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/2257 , H01L21/28525 , H01L21/8222 , H01L29/0804 , H01L29/41708 , H01L29/7322 , Y10S148/011 , Y10S148/124
摘要： A bipolar transistor structure wherein the emitter zone is produced by outward diffusion from etching residues which are formed by deposition of conductive material and re-etching, with the etching residues forming part of the emitter terminal region. In addition to individual transistors, pairs of transistors having coupled emitters can also be produced and employed in hig precision differential amplifiers. Memory cells can also be produced which have low surface requirements, particularly due to the reproduceable attainment of emitter widths below one micron. Since the methods enable the production of completely self-aligned transistors, they can be implemented with straightforward steps which are largely independent of lithography. Emitter widths in the range of about 0.2 to 0.5 microns can be produced.
摘要翻译：一种双极晶体管结构，其中通过由蚀刻残留物向外扩散而产生发射区，该蚀刻残留物是通过沉积导电材料形成的并且重新刻蚀，其中蚀刻残留物形成发射极端区的一部分。除了单独的晶体管，还可以生产具有耦合发射极的晶体管对，并在高精度差分放大器中采用。也可以生产具有低表面要求的记忆单元，特别是由于可重现的发射体宽度低于1微米。由于这些方法能够生产完全自对准的晶体管，所以可以通过简单的步骤实现，这些步骤在很大程度上与光刻无关。可以产生约0.2至0.5微米范围内的发射极宽度。

19. 发明授权

US08143594B2 Method of depositing protective structures 有权
标题翻译：沉积保护结构的方法
公开(公告)号：US08143594B2
公开(公告)日：2012-03-27
申请号：US12658507
申请日：2010-02-05
申请人： Heinz Wanzenboeck , Wolfram Buehler , Holger Doemer , Carl Kuebler , Daniel Fischer , Gottfried Hochleitner , Emmerich Bertagnolli
发明人： Heinz Wanzenboeck , Wolfram Buehler , Holger Doemer , Carl Kuebler , Daniel Fischer , Gottfried Hochleitner , Emmerich Bertagnolli
IPC分类号： G01N1/04 , G21K5/08 , C23C16/48
CPC分类号： G01N1/28 , G01N1/286 , H01J37/26 , H01J37/261 , H01J37/3056 , H01J2237/31745 , H01J2237/31749
摘要： A process of preparing a lamella from a substrate includes manufacturing a protection strip on an edge portion of the lamella to be prepared from the substrate, and preparing the lamella, wherein the manufacturing the protection strip includes a first phase of activating a surface area portion of the substrate, and a second phase of electron beam assisted deposition of the protective strip on the activated surface area portion from the gas phase.
摘要翻译：从衬底制备薄片的方法包括在待从衬底制备的薄片的边缘部分上制造保护条，并制备薄片，其中制造保护条包括激活第一阶段的第一阶段衬底以及电子束辅助沉积在气相的活化表面积部分上的保护带的第二相。

20. 发明授权

US07923702B2 System and method for processing an object 有权
标题翻译：用于处理对象的系统和方法
公开(公告)号：US07923702B2
公开(公告)日：2011-04-12
申请号：US12268802
申请日：2008-11-11
申请人： Wolfram Buhler , Alexander Rosenthal , Emmerich Bertagnolli , Heinz Wanzenbock , Markus Fischer , Gottfried Hochleitner
发明人： Wolfram Buhler , Alexander Rosenthal , Emmerich Bertagnolli , Heinz Wanzenbock , Markus Fischer , Gottfried Hochleitner
IPC分类号： C23C16/458 , C23C16/48 , H01J49/00
CPC分类号： H01J37/3005 , G03F1/74 , G03F1/86 , H01J37/20 , H01J37/3056 , H01J2237/006 , H01J2237/202 , H01J2237/31744
摘要： A system and a method for processing and inspecting an object are provided, wherein the system comprises a particle beam column, an object holder and a gas supply apparatus. Thereby, the object holder is formed comprising a base, a first table displaceable relative to the base, a second table displaceable relative to the first table and a third table rotatable relative to the second table, wherein the cannula of the gas supply apparatus is fixed at the first table.
摘要翻译：提供了一种用于处理和检查物体的系统和方法，其中所述系统包括粒子束柱，物体保持器和气体供应装置。因此，物体保持器形成为包括基部，相对于基部可移动的第一台，相对于第一台可移动的第二台和可相对于第二台转动的第三台，其中气体供应装置的插管固定在第一张桌子

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