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1. 发明授权

US6097049A DRAM cell arrangement 有权
标题翻译： DRAM单元布置
公开(公告)号：US6097049A
公开(公告)日：2000-08-01
申请号：US272077
申请日：1999-03-18
申请人： Bernd Goebel , Eve Marie Martin , Emmerich Bertagnolli
发明人： Bernd Goebel , Eve Marie Martin , Emmerich Bertagnolli
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10852 , H01L27/10823 , H01L27/10876 , Y10S257/906 , Y10S257/907
摘要： A DRAM cell arrangement and method for manufacturing same, wherein a storage capacitor is connected via a first source/drain zone of a vertical selection transistor and a bit line. Since the storage capacitor and the bit line are arranged substantially above a substrate, the bit line can be manufactured of materials having high electrical conductivity, and materials having a high dielectric constant can be utilized for the storage capacitor. At least the first source/drain zone and a channel zone are parts of a projection-like semiconductor structure that is laterally limited by at least two sidewalls. A respective word line can be arranged at the two sidewalls. An element that prevents the drive of the selection transistor by this word line is arranged between the channel zone and one of the word lines. A second source/drain zone of the selection transistor is buried in the substrate and, for example, is part of a doped layer or of a grid-shaped doped region or is connected to the substrate via a buried contact. A memory cell can be manufactured given open bit lines as well as given folded bit lines, wherein it is manufactured with an area of 4F.sup.2.
摘要翻译：一种DRAM单元布置及其制造方法，其中存储电容器经由垂直选择晶体管的第一源极/漏极区域和位线连接。由于存储电容器和位线布置在基板的大致上方，所以位线可以由具有高导电性的材料制造，并且具有高介电常数的材料可用于存储电容器。至少第一源极/漏极区域和沟道区域是由至少两个侧壁横向限制的突起状半导体结构的部分。相应的字线可以布置在两个侧壁处。阻止由该字线驱动选择晶体管的元件被布置在通道区域和一条字线之间。选择晶体管的第二源极/漏极区域被掩埋在衬底中，并且例如是掺杂层或栅格形掺杂区域的一部分，或者通过埋入触点连接到衬底。可以制造给定的开放位线以及给定的折叠位线的存储器单元，其中制造的面积为4F2。

2. 发明授权

US06352894B1 Method of forming DRAM cell arrangement 有权
标题翻译：形成DRAM单元布置的方法
公开(公告)号：US06352894B1
公开(公告)日：2002-03-05
申请号：US09482064
申请日：2000-01-13
申请人： Bernd Goebel , Wolfgang Roesner , Franz Hofmann , Emmerich Bertagnolli , Eve Marie Martin
发明人： Bernd Goebel , Wolfgang Roesner , Franz Hofmann , Emmerich Bertagnolli , Eve Marie Martin
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823 , Y10S257/906 , Y10S438/947
摘要： A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/drain region of a selection transistor and one channel region arranged below the first source/drain region, which is surrounded by a gate electrode annularly. A storage capacitor is connected between the first source/drain region and a bit line. The bit line as well as the storage capacitor are arranged essentially above the semiconductor substrate. Second source/drain regions of selection transistors are buried in the semiconductor substrate and connected with each other. Word lines can be formed self-justified in the form of adjacent gate electrodes. The projections can be created by etching with only one mask. The storage cell can be produced with an area of 4F2, F being the minimal structural size that can be produced in the respective technology.
摘要翻译：存储单元具有排列成行和列的半导体衬底的多个突起，相邻的一列突起相对于平行于列延伸的y轴平移对称。每个突起具有选择晶体管的至少一个第一源极/漏极区域和布置在第一源极/漏极区域下方的一个沟道区域，其被环形的栅极电极包围。存储电容器连接在第一源极/漏极区域和位线之间。位线以及存储电容器基本上布置在半导体衬底的上方。选择晶体管的第二源极/漏极区域被埋在半导体衬底中并彼此连接。字线可以形成为相邻栅电极的形式自对称。可以通过仅使用一个掩模的蚀刻来产生突起。可以生产具有4F2面积的存储单元，F是可以在各自技术中生产的最小结构尺寸。

3. 发明授权

US6044009A DRAM cell arrangement and method for its production 有权
标题翻译： DRAM单元布置及其生产方法
公开(公告)号：US6044009A
公开(公告)日：2000-03-28
申请号：US274733
申请日：1999-03-23
申请人： Bernd Goebel , Wolfgang Roesner , Franz Hofmann , Emmerich Bertagnolli , Eve Marie Martin
发明人： Bernd Goebel , Wolfgang Roesner , Franz Hofmann , Emmerich Bertagnolli , Eve Marie Martin
IPC分类号： H01L21/8242 , H01L27/108 , H01L27/04
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823 , Y10S257/906 , Y10S438/947
摘要： A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/drain region of a selection transistor and one channel region arranged below the first source/drain region, which is surrounded by a gate electrode annularly. A storage capacitor is connected between the first source/drain region and a bit line. The bit line as well as the storage capacitor are arranged essentially above the semiconductor substrate. Second source/drain regions of selection transistors are buried in the semiconductor substrate and connected with each other. Word lines can be formed self-justified in the form of adjacent gate electrodes. The projections can be created by etching with only one mask. The storage cell can be produced with an area of 4F.sup.2, F being the minimal structural size that can be produced in the respective technology.
摘要翻译：存储单元具有排列成行和列的半导体衬底的多个突起，相邻的一列突起相对于平行于列延伸的y轴平移对称。每个突起具有选择晶体管的至少一个第一源极/漏极区域和布置在第一源极/漏极区域下方的一个沟道区域，其被环形的栅极电极包围。存储电容器连接在第一源极/漏极区域和位线之间。位线以及存储电容器基本上布置在半导体衬底的上方。选择晶体管的第二源极/漏极区域被埋在半导体衬底中并彼此连接。字线可以形成为相邻栅电极的形式自对称。可以通过仅使用一个掩模的蚀刻来产生突起。可以生产具有4F2面积的存储单元，F是可以在各自技术中生产的最小结构尺寸。

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