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11. 发明授权

US06433380B1 Integrated circuit capacitors having composite titanium oxide and tantalum pentoxide dielectric layers therein 有权
公开(公告)号：US06433380B1
公开(公告)日：2002-08-13
申请号：US09903153
申请日：2001-07-11
申请人： Dong-won Shin
发明人： Dong-won Shin
IPC分类号： H01L27108
摘要： Methods of forming integrated circuit capacitors (e.g., DRAM capacitors) include the steps of forming a first capacitor electrode (e.g., polysilicon electrode) on a substrate and then forming a titanium nitride layer on the first capacitor electrode. A tantalum pentoxide dielectric layer is then formed on an upper surface of the titanium nitride layer. A step is then performed to convert the underlying titanium nitride layer into a titanium oxide layer. A second capacitor electrode is then formed on the tantalum pentoxide layer. The step of converting the titanium nitride layer into a titanium oxide layer is preferably performed by annealing the tantalum pentoxide layer in an oxygen ambient in a range between about 700° C. and 900° C. This oxygen ambient provides free oxygen to fill vacancies within the tantalum oxide layer and also provides free oxygen which diffuses into the underlying titanium nitride layer.

12. 发明授权

US06300215B1 Methods of forming integrated circuit capacitors having composite titanium oxide and tantalum pentoxide dielectric layers therein 有权
标题翻译：形成具有复合氧化钛和五氧化钽电介质层的集成电路电容器的方法
公开(公告)号：US06300215B1
公开(公告)日：2001-10-09
申请号：US09417859
申请日：1999-10-14
申请人： Dong-won Shin
发明人： Dong-won Shin
IPC分类号： H01L2120
CPC分类号： H01L28/55 , H01L21/31604 , H01L21/31691 , H01L27/10814
摘要： Methods of forming integrated circuit capacitors (e.g., DRAM capacitors) include the steps of forming a first capacitor electrode (e.g., polysilicon electrode) on a substrate and then forming a titanium nitride layer on the first capacitor electrode. A tantalum pentoxide dielectric layer is then formed on an upper surface of the titanium nitride layer. A step is then performed to convert the underlying titanium nitride layer into a titanium oxide layer. A second capacitor electrode is then formed on the tantalum pentoxide layer. The step of converting the titanium nitride layer into a titanium oxide layer is preferably performed by annealing the tantalum pentoxide layer in an oxygen ambient in a range between about 700° C. and 900° C. This oxygen ambient provides free oxygen to fill vacancies within the tantalum oxide layer and also provides free oxygen which diffuses into the underlying titanium nitride layer.
摘要翻译：形成集成电路电容器（例如DRAM电容器）的方法包括以下步骤：在衬底上形成第一电容器电极（例如，多晶硅电极），然后在第一电容器电极上形成氮化钛层。然后在氮化钛层的上表面上形成五氧化二钽介电层。然后进行步骤以将下面的氮化钛层转化为氧化钛层。然后在五氧化二钽层上形成第二电容器电极。将氮化钛层转化为氧化钛层的步骤优选通过在氧气环境中在约700℃和900℃之间的范围内退火五氧化二钽氧化物层来进行。该氧气环境提供游离氧以填补内部的空位氧化钽层，并且还提供扩散到下面的氮化钛层中的游离氧。

13. 发明申请

US20190027675A1 BONDING INTERPOSER AND INTEGRATED CIRCUIT CHIP, AND ULTRASOUND PROBE USING THE SAME 审中-公开
公开(公告)号：US20190027675A1
公开(公告)日：2019-01-24
申请号：US16038348
申请日：2018-07-18
申请人： Dong Won SHIN , SAMSUNG ELECTRONICS CO., LTD.
发明人： Kyung-moo Choi , Dong Won Shin
IPC分类号： H01L41/047 , H01L21/48 , H01L41/25 , H01L23/00 , H01L25/16 , H01L23/538 , H01L41/09 , B06B1/06 , G01N29/24 , A61B8/00
摘要： The method of bonding an interposer and an integrated circuit chip includes preparing an interposer including an insulator and conductive lines each having one end exposed to a first surface of the insulator and another end exposed to a second surface opposite to the first surface; placing a bonding mask on the interposer; forming through-holes on the bonding mask before or after the placing of the bonding mask on the interposer; filling the plurality with a conductive material; and bonding an integrated circuit chip to the bonding mask.

14. 发明授权

US08315080B2 Luminescence device and method of manufacturing the same 有权
标题翻译：发光装置及其制造方法
公开(公告)号：US08315080B2
公开(公告)日：2012-11-20
申请号：US12597168
申请日：2008-04-23
申请人： Jea Gun Park , Gon Sub Lee , Su Hwan Lee , Dal Ho Kim , Sung Ho Seo , Woo Sik Nam , Hyun Min Seung , Jong Dae Lee , Dong Won Shin
发明人： Jea Gun Park , Gon Sub Lee , Su Hwan Lee , Dal Ho Kim , Sung Ho Seo , Woo Sik Nam , Hyun Min Seung , Jong Dae Lee , Dong Won Shin
IPC分类号： G11C13/04
CPC分类号： H05B33/22 , B82Y20/00 , B82Y30/00 , G09G3/2011 , G09G3/3216 , G09G2310/061 , H01L27/26 , H01L27/3244 , H01L51/0591 , H01L51/52 , H01L2251/5338 , H01L2251/5369
摘要： Provided are a luminescent device and a method of manufacturing the same. The luminescent device includes a charge trapping layer having bistable conductance and negative differential resistance (NDR) characteristics, and an organic luminescent layer electrically connected to the charge trapping layer. The charge trapping layer comprise a nanocrystal layer intervened in an organic layer, and the nanocrystal layer comprises a plurality of nanocrystals.
摘要翻译：提供一种发光装置及其制造方法。发光装置包括具有双稳电导和负差分电阻（NDR）特性的电荷捕获层，以及电连接到电荷捕获层的有机发光层。电荷捕获层包括介于有机层中的纳米晶层，并且纳米晶层包含多个纳米晶体。

15. 发明申请

US20100208507A1 LUMINESCENCE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：发光装置及其制造方法
公开(公告)号：US20100208507A1
公开(公告)日：2010-08-19
申请号：US12597168
申请日：2008-04-23
申请人： Jea Gun Park , Gon Sub Lee , Su Hwan Lee , Dal Ho Kim , Sung Ho Seo , Woo Sik Nam , Hyun Min Seung , Jong Dae Lee , Dong Won Shin
发明人： Jea Gun Park , Gon Sub Lee , Su Hwan Lee , Dal Ho Kim , Sung Ho Seo , Woo Sik Nam , Hyun Min Seung , Jong Dae Lee , Dong Won Shin
IPC分类号： G11C13/04 , H01L51/10 , H01L51/40 , G11C7/00
CPC分类号： H05B33/22 , B82Y20/00 , B82Y30/00 , G09G3/2011 , G09G3/3216 , G09G2310/061 , H01L27/26 , H01L27/3244 , H01L51/0591 , H01L51/52 , H01L2251/5338 , H01L2251/5369
摘要： Provided are a luminescent device and a method of manufacturing the same. The luminescent device includes a charge trapping layer having bistable conductance and negative differential resistance (NDR) characteristics, and an organic luminescent layer electrically connected to the charge trapping layer.
摘要翻译：提供一种发光装置及其制造方法。发光装置包括具有双稳电导和负差分电阻（NDR）特性的电荷捕获层，以及电连接到电荷捕获层的有机发光层。

16. 发明授权

US07542518B2 Predistortion apparatus and method for compensating for a nonlinear distortion characteristic of a power amplifier using a look-up table 有权
标题翻译：用于使用查找表补偿功率放大器的非线性失真特性的预失真装置和方法
公开(公告)号：US07542518B2
公开(公告)日：2009-06-02
申请号：US11027676
申请日：2005-01-03
申请人： Dong-Hyun Kim , Dong-Won Shin
发明人： Dong-Hyun Kim , Dong-Won Shin
IPC分类号： H04K1/02
CPC分类号： H04L27/368
摘要： A polynomial predistortion apparatus and method for compensating for a nonlinear distortion characteristic of a power amplifier is provided. The apparatus and method comprise an adaptation controller for determining polynomial coefficients by calculating an inverse nonlinear distortion characteristic of the power amplifier, and calculating complex predistortion gains for all possible amplitudes of an input signal using the determined polynomial coefficients; and a predistorter for receiving an input signal which is a combination of complex-modulated previous baseband input signal samples and current input signal samples, predistorting the input signal using the complex predistortion gains output from the adaptation controller, and outputting the predistorted input signal to the power amplifier.
摘要翻译：提供了一种用于补偿功率放大器的非线性失真特性的多项式预失真装置和方法。该装置和方法包括：一个自适应控制器，用于通过计算功率放大器的反非线性失真特性来确定多项式系数;以及使用所确定的多项式系数来计算输入信号的所有可能振幅的复数预失真增益; 以及预失真器，用于接收作为复调制的先前基带输入信号样本和当前输入信号采样的组合的输入信号，使用从适配控制器输出的复数预失真增益来预失真输入信号，并将预失真输入信号输出到功率放大器。

17. 发明申请

US20060084483A1 Apparatus for playing horse racing game 审中-公开
标题翻译：玩赛马游戏的装置
公开(公告)号：US20060084483A1
公开(公告)日：2006-04-20
申请号：US11195132
申请日：2005-08-02
申请人： Dong Won Shin
发明人： Dong Won Shin
IPC分类号： A63F13/00
CPC分类号： G07F17/32 , G07F17/3288
摘要： A horse racing game apparatus is disclosed, in which a user can easily check a racing information, a statistic information, etc. related with a horse racing and can enjoy a horse racing game in a 3D like an actual horse racing at a horse racing track. The users can play the horse racing game on a large size screen in a 3D like an actual horse racing track, so that high quality services can be provided to the users as compared to the conventional horse racing game apparatus. Various demands of the users which play the horse racing game can be satisfied. As a result, the service company and the development company of the horse racing game can achieve high profits.
摘要翻译：公开了一种赛马游戏装置，其中用户可以容易地检查与赛马相关的赛车信息，统计信息等，并且可以像在赛马场上的实际赛马一样在3D中享受赛马游戏。用户可以像实际的赛马轨迹一样在3D大尺寸屏幕上播放赛马游戏，从而与传统的赛马游戏装置相比，能够向用户提供高品质的服务。满足赛马游戏用户的各种需求。因此，服务公司和赛马游戏开发公司可以实现高利润。

18. 发明授权

US06852581B2 Methods of manufacturing a semiconductor device having increased gaps between gates 有权
标题翻译：制造栅极之间间隙增加的半导体器件的方法
公开(公告)号：US06852581B2
公开(公告)日：2005-02-08
申请号：US10266220
申请日：2002-10-08
申请人： Yoon-soo Chun , Dong-won Shin , Ki-nam Kim
发明人： Yoon-soo Chun , Dong-won Shin , Ki-nam Kim
IPC分类号： H01L27/108 , H01L21/338 , H01L21/4763 , H01L21/768 , H01L21/8242 , H01L27/088 , H01L31/0328
CPC分类号： H01L21/76837 , H01L27/10855 , H01L27/10873 , H01L27/10888 , Y10S257/90
摘要： According to embodiments of the present invention, methods of manufacturing a semiconductor device, and semiconductor devices manufactured thereby, are provided. A field region is formed that defines active regions in a semiconductor substrate. Spaced apart gates are formed on the active regions in the semiconductor substrate. The gates have sidewalls that extend away from the semiconductor substrate. First spacers are formed on the sidewalls of the gates. Second spacers are formed on the first spacers and opposite to the gates. Ion impurities are implanted into the active regions in the semiconductor substrate, adjacent to the gates, using the first and second spacers as an ion implantation mask. A portion of the second spacers is removed to widen the gaps between the gates. A dielectric layer is formed on the semiconductor substrate in the gaps between the gates.
摘要翻译：根据本发明的实施例，提供了制造半导体器件的方法以及由此制造的半导体器件。形成在半导体衬底中限定有源区的场区。间隔开的栅极形成在半导体衬底的有源区上。栅极具有远离半导体衬底延伸的侧壁。第一间隔件形成在门的侧壁上。第二间隔件形成在第一间隔件上并与栅极相对。使用第一和第二间隔物作为离子注入掩模，将离子杂质注入到与栅极相邻的半导体衬底的有源区中。第二间隔件的一部分被去除以加宽门之间的间隙。在栅极之间的间隙中的半导体衬底上形成介电层。

19. 发明授权

US06817638B1 Bumper system 失效
标题翻译：保险杠系统
公开(公告)号：US06817638B1
公开(公告)日：2004-11-16
申请号：US10704878
申请日：2003-11-10
申请人： Won-Jun Choi , Dong-Won Shin , Nam-Hyeong Kim
发明人： Won-Jun Choi , Dong-Won Shin , Nam-Hyeong Kim
IPC分类号： B60R1926
CPC分类号： B60R19/18 , B60R19/04 , B60R2019/1853 , B60R2019/1873
摘要： Disclosed is a bumper system including a bumper cover, an energy absorber formed of a synthetic resin material through a foam molding process, an impact beam for supporting the energy absorber, the impact beam being formed of a glass mat thermoplastic and having a “C”-shaped section, and a stay for connecting the impact beam to a vehicle body. Tips are formed on front upper and lower portions of the impact beam, and a web portion is formed on the impact beam between the tips. Tip insertion grooves in which the tips are inserted are formed on an inner surface of the energy absorber, and a pressure receiving surface corresponding to the web portion is formed on the inner surface of the energy absorber.
摘要翻译：公开了一种保险杠系统，包括保险杠盖，通过泡沫模制工艺由合成树脂材料形成的能量吸收器，用于支撑能量吸收器的冲击梁，所述冲击梁由热塑性塑料制成并具有“C” 形状的部分，以及用于将冲击梁连接到车体的撑杆。尖部形成在冲击梁的前上部和下部，并且腹板部分形成在尖端之间的冲击梁上。在能量吸收体的内表面上形成有插入尖端的尖端插入槽，并且在能量吸收体的内表面上形成有对应于腹板部的受压面。

20. 发明授权

US06642135B2 Method for forming semiconductor memory device having a fuse 失效
标题翻译：一种用于形成具有保险丝的半导体存储器件的方法
公开(公告)号：US06642135B2
公开(公告)日：2003-11-04
申请号：US10283613
申请日：2002-10-29
申请人： Min-Sang Kim , Dong-Won Shin
发明人： Min-Sang Kim , Dong-Won Shin
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L23/5258 , H01L27/10882 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method for forming a semiconductor device having a fuse is provided. A substrate includes a cell array area, a peripheral circuit area and a global step difference between the cell array area and the peripheral circuit area. The substrate comprises a fuse formed in the peripheral circuit of the substrate. An interlayer insulating layer is formed on the global step difference. The global step difference is reduced by a cell open process. A multilevel metal interconnection including an intermetal insulating layer is formed on the resultant structure. During the cell open process and/or the process for forming the multilevel metal interconnection, the interlayer insulating layer and/or the intermetal insulating layer is partially removed to form a recess. A passivation layer is formed on the multilevel metal interconnection. A fuse opening is formed through the recess to expose the fuse. The etching amount for forming the fuse opening is significantly reduced by the partial removal of the interlayer insulating layer and/or the intermetal insulating layer.
摘要翻译：提供一种用于形成具有熔丝的半导体器件的制造方法。基板包括单元阵列区域，外围电路区域和单元阵列区域与外围电路区域之间的全局阶跃差。衬底包括形成在衬底的外围电路中的熔丝。在全局阶差上形成层间绝缘层。通过单元打开过程减少全局步差。在所得结构上形成包括金属间绝缘层的多层金属互连。在电池打开工艺和/或用于形成多层金属互连的工艺中，层间绝缘层和/或金属间绝缘层被部分地去除以形成凹陷。在多层金属互连上形成钝化层。通过凹部形成保险丝开口以露出保险丝。通过部分去除层间绝缘层和/或金属间绝缘层，形成保险丝开口的蚀刻量显着降低。

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