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1. 发明授权

US06852581B2 Methods of manufacturing a semiconductor device having increased gaps between gates 有权
标题翻译：制造栅极之间间隙增加的半导体器件的方法
公开(公告)号：US06852581B2
公开(公告)日：2005-02-08
申请号：US10266220
申请日：2002-10-08
申请人： Yoon-soo Chun , Dong-won Shin , Ki-nam Kim
发明人： Yoon-soo Chun , Dong-won Shin , Ki-nam Kim
IPC分类号： H01L27/108 , H01L21/338 , H01L21/4763 , H01L21/768 , H01L21/8242 , H01L27/088 , H01L31/0328
CPC分类号： H01L21/76837 , H01L27/10855 , H01L27/10873 , H01L27/10888 , Y10S257/90
摘要： According to embodiments of the present invention, methods of manufacturing a semiconductor device, and semiconductor devices manufactured thereby, are provided. A field region is formed that defines active regions in a semiconductor substrate. Spaced apart gates are formed on the active regions in the semiconductor substrate. The gates have sidewalls that extend away from the semiconductor substrate. First spacers are formed on the sidewalls of the gates. Second spacers are formed on the first spacers and opposite to the gates. Ion impurities are implanted into the active regions in the semiconductor substrate, adjacent to the gates, using the first and second spacers as an ion implantation mask. A portion of the second spacers is removed to widen the gaps between the gates. A dielectric layer is formed on the semiconductor substrate in the gaps between the gates.
摘要翻译：根据本发明的实施例，提供了制造半导体器件的方法以及由此制造的半导体器件。形成在半导体衬底中限定有源区的场区。间隔开的栅极形成在半导体衬底的有源区上。栅极具有远离半导体衬底延伸的侧壁。第一间隔件形成在门的侧壁上。第二间隔件形成在第一间隔件上并与栅极相对。使用第一和第二间隔物作为离子注入掩模，将离子杂质注入到与栅极相邻的半导体衬底的有源区中。第二间隔件的一部分被去除以加宽门之间的间隙。在栅极之间的间隙中的半导体衬底上形成介电层。

2. 发明授权

US06911740B2 Semiconductor device having increased gaps between gates 有权
标题翻译：具有增加的栅极间隙的半导体器件
公开(公告)号：US06911740B2
公开(公告)日：2005-06-28
申请号：US10847652
申请日：2004-05-17
申请人： Yoon-soo Chun , Dong-won Shin , Ki-nam Kim
发明人： Yoon-soo Chun , Dong-won Shin , Ki-nam Kim
IPC分类号： H01L27/108 , H01L21/338 , H01L21/4763 , H01L21/768 , H01L21/8242 , H01L27/088 , H01L31/0328
CPC分类号： H01L21/76837 , H01L27/10855 , H01L27/10873 , H01L27/10888 , Y10S257/90
摘要： According to embodiments of the present invention, methods of manufacturing a semiconductor device, and semiconductor devices manufactured thereby, are provided. A field region is formed that defines active regions in a semiconductor substrate. Spaced apart gates are formed on the active regions in the semiconductor substrate. The gates have sidewalls that extend away from the semiconductor substrate. First spacers are formed on the sidewalls of the gates. Second spacers are formed on the first spacers and opposite to the gates. Ion impurities are implanted into the active regions in the semiconductor substrate, adjacent to the gates, using the first and second spacers as an ion implantation mask. A portion of the second spacers is removed to widen the gaps between the gates. A dielectric layer is formed on the semiconductor substrate in the gaps between the gates.
摘要翻译：根据本发明的实施例，提供了制造半导体器件的方法以及由此制造的半导体器件。形成在半导体衬底中限定有源区的场区。间隔开的栅极形成在半导体衬底的有源区上。栅极具有远离半导体衬底延伸的侧壁。第一间隔件形成在门的侧壁上。第二间隔件形成在第一间隔件上并与栅极相对。使用第一和第二间隔物作为离子注入掩模，将离子杂质注入到与栅极相邻的半导体衬底的有源区中。第二间隔件的一部分被去除以加宽门之间的间隙。在栅极之间的间隙中的半导体衬底上形成介电层。

3. 发明授权

US6069817A Memory device evaluation methods using test capacitor patterns 失效
标题翻译：使用测试电容器图案的存储器件评估方法
公开(公告)号：US6069817A
公开(公告)日：2000-05-30
申请号：US201694
申请日：1998-11-30
申请人： Dong-won Shin , Jin-woo Lee
发明人： Dong-won Shin , Jin-woo Lee
IPC分类号： H01L21/66 , G11C11/22 , G11C29/02 , G11C29/12 , G11C29/50
CPC分类号： G11C29/026 , G11C11/22 , G11C29/02 , G11C29/50 , G11C2029/5004
摘要： A ferroelectric memory device formed on a microelectronic substrate is evaluated. The memory device includes a sense amplifier and a plurality of ferroelectric capacitors that are operatively connected to the sense amplifier to read information stored in the ferroelectric capacitors. A plurality of test ferroelectric capacitors is formed on the microelectronic substrate. Polarization characteristics are determined for the plurality of test ferroelectric capacitors. An input to the sense amplifier is estimated from the determined polarization characteristics, and the ferroelectric memory device is evaluated based on the estimated input. The estimated input may be compared to an input criterion, e.g., a minimum sensing charge or voltage for the sense amplifier, and the ferroelectric memory device may be either rejected or subjected to further testing depending on whether the estimated input fails to meet or meets the input criterion.
摘要翻译：评估形成在微电子基板上的铁电存储器件。存储器件包括读出放大器和可操作地连接到读出放大器以读取存储在铁电电容器中的信息的多个铁电电容器。在微电子基板上形成多个测试铁电电容器。确定多个测试铁电电容器的极化特性。根据确定的极化特性估计读出放大器的输入，并且基于估计的输入来评估铁电存储器件。估计的输入可以与输入标准进行比较，例如，感测放大器的最小感测电荷或电压，并且铁电存储器件可以被拒绝或进行进一步的测试，这取决于估计的输入是否满足或满足输入标准。

4. 发明授权

US06730956B2 Method for manufacturing the storage node of a capacitor of a semiconductor device and a storage node manufactured by the method 失效
标题翻译：用于制造半导体器件的电容器的存储节点的方法和通过该方法制造的存储节点
公开(公告)号：US06730956B2
公开(公告)日：2004-05-04
申请号：US10329488
申请日：2002-12-27
申请人： Dong-il Bae , Dong-won Shin , Sang-hyeon Lee
发明人： Dong-il Bae , Dong-won Shin , Sang-hyeon Lee
IPC分类号： H01L27108
CPC分类号： H01L28/91 , H01L27/10852
摘要： Methods for manufacturing a storage node of a capacitor of a semiconductor device and a storage node manufactured by these methods are provided. An exemplary method for manufacturing a storage node of a capacitor of a semiconductor device includes forming a mold layer on a semiconductor substrate, forming a mold for the storage node by patterning the mold layer by a photolithography process, introducing a photomask which includes a plurality of light transmitting patterns separated from each other and which define the region to be occupied by the storage node, and forming a storage node that has the shape formed by the mold. The photolithography process is performed with the occurrence of a pattern bridge phenomenon, e.g., the transferred light transmitting patterns are connected to each other in a pattern transferred from the light transmitting patterns to the mold.
摘要翻译：提供了通过这些方法制造半导体器件的电容器的存储节点和存储节点的方法。用于制造半导体器件的电容器的存储节点的示例性方法包括在半导体衬底上形成模具层，通过光刻工艺对模具层进行图案化形成用于存储节点的模具，引入包括多个光传输图案彼此分离并且限定要由存储节点占据的区域，以及形成具有由模具形成的形状的存储节点。光刻工艺是在出现图形桥现象的情况下进行的，例如，转印的光透射图案以从透光图案转印到模具的图案彼此连接。

5. 发明授权

US06433380B1 Integrated circuit capacitors having composite titanium oxide and tantalum pentoxide dielectric layers therein 有权
公开(公告)号：US06433380B1
公开(公告)日：2002-08-13
申请号：US09903153
申请日：2001-07-11
申请人： Dong-won Shin
发明人： Dong-won Shin
IPC分类号： H01L27108
摘要： Methods of forming integrated circuit capacitors (e.g., DRAM capacitors) include the steps of forming a first capacitor electrode (e.g., polysilicon electrode) on a substrate and then forming a titanium nitride layer on the first capacitor electrode. A tantalum pentoxide dielectric layer is then formed on an upper surface of the titanium nitride layer. A step is then performed to convert the underlying titanium nitride layer into a titanium oxide layer. A second capacitor electrode is then formed on the tantalum pentoxide layer. The step of converting the titanium nitride layer into a titanium oxide layer is preferably performed by annealing the tantalum pentoxide layer in an oxygen ambient in a range between about 700° C. and 900° C. This oxygen ambient provides free oxygen to fill vacancies within the tantalum oxide layer and also provides free oxygen which diffuses into the underlying titanium nitride layer.

6. 发明授权

US06300215B1 Methods of forming integrated circuit capacitors having composite titanium oxide and tantalum pentoxide dielectric layers therein 有权
标题翻译：形成具有复合氧化钛和五氧化钽电介质层的集成电路电容器的方法
公开(公告)号：US06300215B1
公开(公告)日：2001-10-09
申请号：US09417859
申请日：1999-10-14
申请人： Dong-won Shin
发明人： Dong-won Shin
IPC分类号： H01L2120
CPC分类号： H01L28/55 , H01L21/31604 , H01L21/31691 , H01L27/10814
摘要： Methods of forming integrated circuit capacitors (e.g., DRAM capacitors) include the steps of forming a first capacitor electrode (e.g., polysilicon electrode) on a substrate and then forming a titanium nitride layer on the first capacitor electrode. A tantalum pentoxide dielectric layer is then formed on an upper surface of the titanium nitride layer. A step is then performed to convert the underlying titanium nitride layer into a titanium oxide layer. A second capacitor electrode is then formed on the tantalum pentoxide layer. The step of converting the titanium nitride layer into a titanium oxide layer is preferably performed by annealing the tantalum pentoxide layer in an oxygen ambient in a range between about 700° C. and 900° C. This oxygen ambient provides free oxygen to fill vacancies within the tantalum oxide layer and also provides free oxygen which diffuses into the underlying titanium nitride layer.
摘要翻译：形成集成电路电容器（例如DRAM电容器）的方法包括以下步骤：在衬底上形成第一电容器电极（例如，多晶硅电极），然后在第一电容器电极上形成氮化钛层。然后在氮化钛层的上表面上形成五氧化二钽介电层。然后进行步骤以将下面的氮化钛层转化为氧化钛层。然后在五氧化二钽层上形成第二电容器电极。将氮化钛层转化为氧化钛层的步骤优选通过在氧气环境中在约700℃和900℃之间的范围内退火五氧化二钽氧化物层来进行。该氧气环境提供游离氧以填补内部的空位氧化钽层，并且还提供扩散到下面的氮化钛层中的游离氧。

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