专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20080122059A1 STACKED CHIP PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：堆叠芯片包装结构及其制作方法
公开(公告)号：US20080122059A1
公开(公告)日：2008-05-29
申请号：US11839290
申请日：2007-08-15
申请人： Che-Ya Chou , Chih-Pin Hung
发明人： Che-Ya Chou , Chih-Pin Hung
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2924/00011 , H01L2924/00014 , H01L2924/01033 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/0401
摘要： A stacked chip package structure including a carrier, a first chip, a second chip, a barrier layer, and a metal piece is provided. The carrier has an upper surface and a corresponding lower surface. The first chip is disposed on the upper surface of the carrier, and electrically connected to the carrier. The second chip is disposed over the first chip, and electrically connected to the carrier. The barrier layer is made of an electrically conductive material, and is disposed between the first chip and the second chip. The metal piece is connected to a border of the barrier layer, and electrically connected to a ground, such that the barrier layer is grounded via the metal piece. A fabricating method of the stacked chip package structure is also provided.
摘要翻译：提供了包括载体，第一芯片，第二芯片，阻挡层和金属片的堆叠芯片封装结构。载体具有上表面和相应的下表面。第一芯片设置在载体的上表面上，并与载体电连接。第二芯片设置在第一芯片上，并且电连接到载体。阻挡层由导电材料制成，并且设置在第一芯片和第二芯片之间。金属片连接到阻挡层的边界，并且电连接到地，使得阻挡层通过金属片接地。还提供了一种堆叠芯片封装结构的制造方法。

12. 发明授权

US06828664B2 Packaging substrate with electrostatic discharge protection 有权
标题翻译：包装基板采用静电放电保护
公开(公告)号：US06828664B2
公开(公告)日：2004-12-07
申请号：US10282422
申请日：2002-10-29
申请人： Chih-Pin Hung , Yung-Chi Lee
发明人： Chih-Pin Hung , Yung-Chi Lee
IPC分类号： H01L2302
CPC分类号： H01L23/60 , H01L21/565 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a packaging substrate with electrostatic discharge protection. The packaging substrate is disposed in a recess of a mold and comprises an outer wall electrically connecting an inner wall of the recess. A first copper-mesh layer and a second copper-mesh layer extend to the outer wall to electrically connect the inner wall of the recess. Static electric charges generated during the molding process are conducted via the first copper-mesh layer or the second copper-mesh layer to the inner wall of the recess and then conducted away. Therefore, the static electric charges generated during the molding process can be safely conducted away from the packaging substrate, preventing the dies to be packaged from damage due to electrostatic discharge so as to raise the yield rate of semiconductor package products.
摘要翻译：本发明涉及具有静电放电保护的封装基板。包装衬底设置在模具的凹部中，并且包括电连接凹部的内壁的外壁。第一铜网层和第二铜网层延伸到外壁以电连接凹部的内壁。在模制过程中产生的静电荷通过第一铜网层或第二铜网层进入凹槽的内壁，然后导电。因此，可以将成型工序中产生的静电电荷从封装基板安全地导入，从而防止由于静电放电而使芯片受到损坏，从而提高半导体封装产品的成品率。

13. 发明授权

US07944707B2 Package structure for connection with output/input module 有权
标题翻译：与输出/输入模块连接的封装结构
公开(公告)号：US07944707B2
公开(公告)日：2011-05-17
申请号：US12030565
申请日：2008-02-13
申请人： Chih-pin Hung , Ying-te Ou
发明人： Chih-pin Hung , Ying-te Ou
IPC分类号： H05K1/18
CPC分类号： H05K1/117 , H01L23/13 , H01L23/5383 , H01L2924/15153 , H01L2924/1517 , H05K3/366 , H05K2201/048 , H05K2201/09036 , H05K2201/09163 , H05K2203/0307
摘要： A package structure for connection with an output/input module is disclosed. The package structure can be applied to conventional multi-chip packages and system in packages. The package structure defines at least one insertion cavity that is vertically or horizontally disposed. By simply inserting an output/input module into the insertion cavity, an electrical connection can be established between the output/input module and the package structure. Accordingly, the package structure thus constructed can address the repairing, replacement and upgrading problems of electronic components encountered by a package structure that adopts the conventional soldering connection method.
摘要翻译：公开了一种用于与输出/输入模块连接的封装结构。封装结构可以应用于传统的多芯片封装和封装中的系统。包装结构限定了垂直或水平设置的至少一个插入腔。通过简单地将输出/输入模块插入到插入腔中，可以在输出/输入模块和封装结构之间建立电连接。因此，如此构造的封装结构可以解决采用常规焊接连接方法的封装结构所遇到的电子部件的修理，更换和升级问题。

14. 发明申请

US20100265009A1 STACKED LC RESONATOR AND BANDPASS FILTER OF USING THE SAME 审中-公开
标题翻译：堆叠式LC谐振器和使用它的BANDPASS滤波器
公开(公告)号：US20100265009A1
公开(公告)日：2010-10-21
申请号：US12425045
申请日：2009-04-16
申请人： Tzyy-Sheng Horng , Chien-Hsun Chen , Chien-Hsiang Huang , Sung-Mao Wu , Chi-Tsung Chiu , Chih-Pin Hung
发明人： Tzyy-Sheng Horng , Chien-Hsun Chen , Chien-Hsiang Huang , Sung-Mao Wu , Chi-Tsung Chiu , Chih-Pin Hung
IPC分类号： H03H7/01 , H03H7/12
CPC分类号： H03H7/0115 , H03H2001/0085
摘要： A stacked LC resonator includes a parallel-plate capacitor, a dielectric layer and a spiral inductor. The parallel-plate capacitor has a first metal layer, a second metal layer opposed to the first metal layer and a middle dielectric layer formed between the first and second metal layers. The dielectric layer is formed on the second metal layer of the parallel-plate capacitor. The spiral inductor is formed on the dielectric layer and electrically connected with the first and second metal layers of the parallel-plate capacitor.
摘要翻译：叠层LC谐振器包括平行板电容器，电介质层和螺旋电感器。平行板电容器具有第一金属层，与第一金属层相对的第二金属层和形成在第一和第二金属层之间的中间介电层。电介质层形成在平行板电容器的第二金属层上。螺旋电感器形成在电介质层上并与平行板电容器的第一和第二金属层电连接。

15. 发明申请

US20090256244A1 SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING 有权
标题翻译：具有电磁干扰屏蔽的半导体器件封装
公开(公告)号：US20090256244A1
公开(公告)日：2009-10-15
申请号：US12489115
申请日：2009-06-22
申请人： Kuo-Hsien Liao , Chi-Tsung Chiu , Chih-Pin Hung
发明人： Kuo-Hsien Liao , Chi-Tsung Chiu , Chih-Pin Hung
IPC分类号： H01L23/552 , H01L21/56
CPC分类号： H01L23/552 , H01L21/568 , H01L21/6835 , H01L23/3121 , H01L23/49805 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2221/68345 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/81005 , H01L2224/85005 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , Y10T29/49146 , Y10T29/49153 , Y10T29/49165 , Y10T29/49789 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of an internal grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.
摘要翻译：这里描述的是具有EMI屏蔽和相关方法的半导体器件封装。在一个实施例中，半导体器件封装包括：（1）包括接地元件的衬底单元; （2）设置在所述衬底单元的上表面附近的半导体器件; （3）与基板单元的上表面相邻并且覆盖半导体器件的封装体; 和（4）EMI封装体，其与所述封装主体的外表面相邻地设置并电连接到所述接地元件的连接表面。封装主体的侧表面基本上与衬底单元的侧表面对准，并且接地元件的连接表面邻近衬底单元的侧表面电暴露。接地元件对应于内部接地通孔的残留物，并且提供了入射到EMI屏蔽层上的接地电磁辐射的电气路径。

16. 发明申请

US20080218981A1 PACKAGE STRUCTURE FOR CONNECTION WITH OUTPUT/INPUT MODULE 有权
标题翻译：用于连接输出/输入模块的封装结构
公开(公告)号：US20080218981A1
公开(公告)日：2008-09-11
申请号：US12030565
申请日：2008-02-13
申请人： Chih-pin Hung , Ying-te Ou
发明人： Chih-pin Hung , Ying-te Ou
IPC分类号： H05K7/00
CPC分类号： H05K1/117 , H01L23/13 , H01L23/5383 , H01L2924/15153 , H01L2924/1517 , H05K3/366 , H05K2201/048 , H05K2201/09036 , H05K2201/09163 , H05K2203/0307
摘要： A package structure for connection with an output/input module is disclosed. The package structure can be applied to conventional multi-chip packages and system in packages. The package structure defines at least one insertion cavity that is vertically or horizontally disposed. By simply inserting an output/input module into the insertion cavity, an electrical connection can be established between the output/input module and the package structure. Accordingly, the package structure thus constructed can address the repairing, replacement and upgrading problems of electronic components encountered by a package structure that adopts the conventional soldering connection method.
摘要翻译：公开了一种用于与输出/输入模块连接的封装结构。封装结构可以应用于传统的多芯片封装和封装中的系统。包装结构限定了垂直或水平设置的至少一个插入腔。通过简单地将输出/输入模块插入到插入腔中，可以在输出/输入模块和封装结构之间建立电连接。因此，如此构造的封装结构可以解决采用常规焊接连接方法的封装结构所遇到的电子部件的修理，更换和升级问题。

17. 发明申请

US20080054460A1 STRUCTURE OF WAFER LEVEL PACKAGE WITH AREA BUMP 有权
标题翻译： WAFER LEVEL PACKAGE WITH AREA BUMP的结构
公开(公告)号：US20080054460A1
公开(公告)日：2008-03-06
申请号：US11934793
申请日：2007-11-05
申请人： Chih-Pin Hung
发明人： Chih-Pin Hung
IPC分类号： H01L23/48
CPC分类号： H01L23/3107 , H01L21/561 , H01L21/563 , H01L23/3114 , H01L23/49816 , H01L23/49838 , H01L23/5389 , H01L23/544 , H01L24/13 , H01L24/14 , H01L24/17 , H01L2223/54433 , H01L2223/54473 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05552 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/0603 , H01L2224/06051 , H01L2224/13099 , H01L2224/1403 , H01L2224/14051 , H01L2224/73203 , H01L2224/73204 , H01L2224/82039 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/181 , H01L2924/19015 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： A package structure with an area bump has at least a chip (also known as a die), a redistribution layer, a plurality of first bumps (normal bumps) and at least a second bump (area bump). The redistribution layer may reroute and integrate the bonding pads of the chip and incorporate the passive components therein.
摘要翻译：具有区域凸块的封装结构至少具有芯片（也称为裸片），再分配层，多个第一凸块（正常凸块）和至少第二凸块（区域凸块）。再分配层可以重新路由并集成芯片的接合焊盘并且将无源组件并入其中。

18. 发明申请

US20080054450A1 CHIP PACKAGE STRUCTURE AND HEAT SINK FOR CHIP PACKAGE 审中-公开
标题翻译：芯片包装结构和散热片用于芯片包装
公开(公告)号：US20080054450A1
公开(公告)日：2008-03-06
申请号：US11831412
申请日：2007-07-31
申请人： Chi-Tsung Chiu , Chih-Pin Hung , Ying-Te Ou
发明人： Chi-Tsung Chiu , Chih-Pin Hung , Ying-Te Ou
IPC分类号： H01L23/34 , H05K7/20
CPC分类号： H01L23/367 , H01L23/64 , H01L2924/0002 , H01L2924/00
摘要： A chip package structure including a circuit substrate, a chip, a heat sink, and at least one electrical connector is provided. The circuit substrate has a carrying surface and at least one contact disposed on the carrying surface. The chip is disposed on the carrying surface and electrically connected to the circuit substrate. The heat sink is disposed on the carrying surface and includes a thermal conductive body, at least one passive device, and at least one electrical conductive terminal. The thermal conductive body has a bonding surface and the passive device is embedded in the thermal conductive body. The electrical conductive terminal is connected to the passive device. The electrical connector is disposed between the electrical conductive terminal and the corresponding contact, such that the circuit substrate is electrically connected to the passive device. Since the passive device is disposed in the heat sink, the layout space is increased.
摘要翻译：提供了包括电路基板，芯片，散热器和至少一个电连接器的芯片封装结构。电路基板具有承载表面和设置在承载表面上的至少一个触点。芯片设置在承载表面上并电连接到电路基板。散热器设置在承载表面上并且包括导热体，至少一个无源器件和至少一个导电端子。导热体具有接合表面，并且无源器件嵌入在导热体中。导电端子连接到无源器件。电连接器设置在导电端子和对应的触点之间，使得电路基板电连接到无源器件。由于无源器件设置在散热器中，因此布局空间增加。

19. 发明授权

US07312102B2 Bridge connection type of chip package and fabricating method thereof 有权
标题翻译：芯片封装的桥接型及其制造方法
公开(公告)号：US07312102B2
公开(公告)日：2007-12-25
申请号：US10904423
申请日：2004-11-10
申请人： Chih-Pin Hung
发明人： Chih-Pin Hung
IPC分类号： H01L21/00
CPC分类号： H01L23/5389 , H01L23/49816 , H01L24/24 , H01L24/48 , H01L24/73 , H01L24/82 , H01L2224/24227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/00015 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399 , H01L2224/45015 , H01L2924/207
摘要： A chip package having at least a substrate, a chip and a conductive trace is provided. The substrate has a first surface, a second surface, a cavity and at least one substrate contact all positioned on the first surface of the substrate. The chip has an active surface with at least one chip contact thereon. The chip is accommodated inside the cavity with at least one sidewall having contact with one of the sidewalls of the cavity. The active surface of the chip and the first surface of the substrate are coplanar. The conductive trace runs from the active surface of the chip to the first surface of the substrate so that the chip contact and the substrate contact are electrically connected.
摘要翻译：提供了至少具有基板，芯片和导电迹线的芯片封装。衬底具有全部位于衬底的第一表面上的第一表面，第二表面，空腔和至少一个衬底接触。该芯片具有在其上具有至少一个芯片接触的有源表面。芯片容纳在腔内，具有与空腔的一个侧壁接触的至少一个侧壁。芯片的有源表面和基板的第一表面是共面的。导电迹线从芯片的有源表面延伸到基板的第一表面，使得芯片触点和基板触点电连接。

20. 发明申请

US20060103483A1 Inductor and capacitor formed of build-up vias 有权
标题翻译：由积聚通孔形成的电感和电容器
公开(公告)号：US20060103483A1
公开(公告)日：2006-05-18
申请号：US11186859
申请日：2005-07-22
申请人： Sung-Mao Wu , Chi-Tsung Chiu , Chih-Pin Hung
发明人： Sung-Mao Wu , Chi-Tsung Chiu , Chih-Pin Hung
IPC分类号： H03H5/02
CPC分类号： H05K1/0216 , H01G4/236 , H05K1/025 , H05K1/162 , H05K1/165 , H05K2201/09509
摘要： An inductor and capacitor implemented with build-up vias. The inductor and capacitor comprise a conductor plane, a dielectric layer, an inductor/capacitor inducing build-up via and a conductor layer. There is a conducting material in the inductor/capacitor inducing build-up via and a fist end thereof is in contact with the conductor plane. The length of the inductor inducing build-up via is larger than one fourth of a signal wavelength while the length of the conductor inducing build-up via is smaller than one fourth of a signal wavelength.
摘要翻译：用积层通孔实现的电感和电容器。电感器和电容器包括导体平面，电介质层，电感器/电容器，用于引导积聚通孔和导体层。在电感器/电容器中存在导电材料，其导致积聚通孔，并且其第一端与导体平面接触。感应电感通孔的电感长度大于信号波长的四分之一，而导体积聚通孔的导体长度小于信号波长的四分之一。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式