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1. 发明申请

US20080054450A1 CHIP PACKAGE STRUCTURE AND HEAT SINK FOR CHIP PACKAGE 审中-公开
标题翻译：芯片包装结构和散热片用于芯片包装
公开(公告)号：US20080054450A1
公开(公告)日：2008-03-06
申请号：US11831412
申请日：2007-07-31
申请人： Chi-Tsung Chiu , Chih-Pin Hung , Ying-Te Ou
发明人： Chi-Tsung Chiu , Chih-Pin Hung , Ying-Te Ou
IPC分类号： H01L23/34 , H05K7/20
CPC分类号： H01L23/367 , H01L23/64 , H01L2924/0002 , H01L2924/00
摘要： A chip package structure including a circuit substrate, a chip, a heat sink, and at least one electrical connector is provided. The circuit substrate has a carrying surface and at least one contact disposed on the carrying surface. The chip is disposed on the carrying surface and electrically connected to the circuit substrate. The heat sink is disposed on the carrying surface and includes a thermal conductive body, at least one passive device, and at least one electrical conductive terminal. The thermal conductive body has a bonding surface and the passive device is embedded in the thermal conductive body. The electrical conductive terminal is connected to the passive device. The electrical connector is disposed between the electrical conductive terminal and the corresponding contact, such that the circuit substrate is electrically connected to the passive device. Since the passive device is disposed in the heat sink, the layout space is increased.
摘要翻译：提供了包括电路基板，芯片，散热器和至少一个电连接器的芯片封装结构。电路基板具有承载表面和设置在承载表面上的至少一个触点。芯片设置在承载表面上并电连接到电路基板。散热器设置在承载表面上并且包括导热体，至少一个无源器件和至少一个导电端子。导热体具有接合表面，并且无源器件嵌入在导热体中。导电端子连接到无源器件。电连接器设置在导电端子和对应的触点之间，使得电路基板电连接到无源器件。由于无源器件设置在散热器中，因此布局空间增加。

2. 发明授权

US08486829B2 Semiconductor element having a conductive via and method for making the same and package having a semiconductor element with a conductive via 有权
标题翻译：具有导电通孔的半导体元件及其制造方法以及具有导电通孔的半导体元件的封装
公开(公告)号：US08486829B2
公开(公告)日：2013-07-16
申请号：US13720559
申请日：2012-12-19
申请人： Chi-Tsung Chiu , Ying-Te Ou , Meng-Jen Wang
发明人： Chi-Tsung Chiu , Ying-Te Ou , Meng-Jen Wang
IPC分类号： H01L21/44
CPC分类号： H01L21/486 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/13099 , H01L2224/131 , H01L2224/16146 , H01L2224/16225 , H01L2224/32145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/12044 , H01L2924/15311 , H01L2924/157 , H01L2924/181 , H01L2924/00 , H01L2224/05552
摘要： The present invention relates to a semiconductor element having a conductive via and a method for making the same and a package having a semiconductor element with a conductive via. The semiconductor element includes a silicon chip and at least one conductive via. The silicon chip includes a silicon substrate and an active circuit layer. The active circuit layer is disposed on a second surface of the silicon substrate, and has at least one metal layer. The conductive via penetrates the silicon substrate, and includes a conductive metal, The conductive metal electrically connects to the metal layer of the active circuit layer, and a surface of the conductive metal is exposed to the outside of a first surface of the silicon substrate. Therefore, a chip is able to be directly stacked on the semiconductor element without forming a passivation layer and a redistribution layer on the first surface of the silicon substrate, and the process is simplified and the manufacturing cost is decreased.
摘要翻译：本发明涉及具有导电通孔的半导体元件及其制造方法以及具有导电通孔的半导体元件的封装。半导体元件包括硅芯片和至少一个导电通孔。硅芯片包括硅衬底和有源电路层。有源电路层设置在硅衬底的第二表面上，并具有至少一个金属层。导电通孔穿透硅衬底，并且包括导电金属。导电金属电连接到有源电路层的金属层，并且导电金属的表面暴露于硅衬底的第一表面的外部。因此，芯片能够直接层叠在半导体元件上，而不在硅衬底的第一表面上形成钝化层和再分布层，并且简化了工艺，降低了制造成本。

3. 发明授权

US08350361B2 Semiconductor element having a conductive via and method for making the same and package having a semiconductor element with a conductive via 有权
标题翻译：具有导电通孔的半导体元件及其制造方法以及具有导电通孔的半导体元件的封装
公开(公告)号：US08350361B2
公开(公告)日：2013-01-08
申请号：US12830964
申请日：2010-07-06
申请人： Chi-Tsung Chiu , Ying-Te Ou , Meng-Jen Wang
发明人： Chi-Tsung Chiu , Ying-Te Ou , Meng-Jen Wang
IPC分类号： H01L29/40
CPC分类号： H01L21/486 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/13099 , H01L2224/131 , H01L2224/16146 , H01L2224/16225 , H01L2224/32145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/12044 , H01L2924/15311 , H01L2924/157 , H01L2924/181 , H01L2924/00 , H01L2224/05552
摘要： The present invention relates to a semiconductor element having a conductive via and a method for making the same and a package having a semiconductor element with a conductive via. The semiconductor element includes a silicon chip and at least one conductive via. The silicon chip includes a silicon substrate and an active circuit layer. The active circuit layer is disposed on a second surface of the silicon substrate, and has at least one metal layer. The conductive via penetrates the silicon substrate, and includes a conductive metal. The conductive metal electrically connects to the metal layer of the active circuit layer, and a surface of the conductive metal is exposed to the outside of a first surface of the silicon substrate. Therefore, a chip is able to be directly stacked on the semiconductor element without forming a passivation layer and a redistribution layer on the first surface of the silicon substrate, and the process is simplified and the manufacturing cost is decreased.
摘要翻译：本发明涉及具有导电通孔的半导体元件及其制造方法以及具有导电通孔的半导体元件的封装。半导体元件包括硅芯片和至少一个导电通孔。硅芯片包括硅衬底和有源电路层。有源电路层设置在硅衬底的第二表面上，并具有至少一个金属层。导电通孔穿透硅衬底，并且包括导电金属。导电金属电连接到有源电路层的金属层，并且导电金属的表面暴露于硅衬底的第一表面的外侧。因此，芯片能够直接层叠在半导体元件上，而不在硅衬底的第一表面上形成钝化层和再分布层，并且简化了工艺，降低了制造成本。

4. 发明申请

US20110068437A1 Semiconductor Element Having a Conductive Via and Method for Making the Same and Package Having a Semiconductor Element with a Conductive Via 有权
标题翻译：具有导电通孔的半导体元件及其制造方法以及具有导电通孔的半导体元件的封装
公开(公告)号：US20110068437A1
公开(公告)日：2011-03-24
申请号：US12830964
申请日：2010-07-06
申请人： Chi-Tsung Chiu , Ying-Te Ou , Meng-Jen Wang
发明人： Chi-Tsung Chiu , Ying-Te Ou , Meng-Jen Wang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/486 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/13099 , H01L2224/131 , H01L2224/16146 , H01L2224/16225 , H01L2224/32145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/12044 , H01L2924/15311 , H01L2924/157 , H01L2924/181 , H01L2924/00 , H01L2224/05552
摘要： The present invention relates to a semiconductor element having a conductive via and a method for making the same and a package having a semiconductor element with a conductive via. The semiconductor element includes a silicon chip and at least one conductive via. The silicon chip includes a silicon substrate and an active circuit layer. The active circuit layer is disposed on a second surface of the silicon substrate, and has at least one metal layer. The conductive via penetrates the silicon substrate, and includes a conductive metal. The conductive metal electrically connects to the metal layer of the active circuit layer, and a surface of the conductive metal is exposed to the outside of a first surface of the silicon substrate. Therefore, a chip is able to be directly stacked on the semiconductor element without forming a passivation layer and a redistribution layer on the first surface of the silicon substrate, and the process is simplified and the manufacturing cost is decreased.
摘要翻译：本发明涉及具有导电通孔的半导体元件及其制造方法以及具有导电通孔的半导体元件的封装。半导体元件包括硅芯片和至少一个导电通孔。硅芯片包括硅衬底和有源电路层。有源电路层设置在硅衬底的第二表面上，并具有至少一个金属层。导电通孔穿透硅衬底，并且包括导电金属。导电金属电连接到有源电路层的金属层，并且导电金属的表面暴露于硅衬底的第一表面的外侧。因此，芯片能够直接层叠在半导体元件上，而不在硅衬底的第一表面上形成钝化层和再分布层，并且简化了工艺，降低了制造成本。

5. 发明授权

US08212339B2 Semiconductor device packages with electromagnetic interference shielding 有权
标题翻译：具有电磁干扰屏蔽的半导体器件封装
公开(公告)号：US08212339B2
公开(公告)日：2012-07-03
申请号：US12770645
申请日：2010-04-29
申请人： Kuo-Hsien Liao , Jian-Cheng Chen , Chen-Chuan Fan , Chi-Tsung Chiu , Chih-Pin Hung
发明人： Kuo-Hsien Liao , Jian-Cheng Chen , Chen-Chuan Fan , Chi-Tsung Chiu , Chih-Pin Hung
IPC分类号： H01L23/552 , H01L21/78
CPC分类号： H01L23/552 , H01L21/6835 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2221/68331 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.
摘要翻译：这里描述的是具有EMI屏蔽和相关方法的半导体器件封装。在一个实施例中，半导体器件封装包括邻近衬底单元的周边设置并至少部分地在衬底单元的上表面和下表面之间延伸的接地元件。接地元件包括与衬底单元的侧表面相邻设置的凹入部分。半导体器件封装还包括EMI屏蔽，其电连接到接地元件并且与接地元件的凹入部分相邻地向内凹陷。

6. 发明授权

US08022511B2 Semiconductor device packages with electromagnetic interference shielding 有权
标题翻译：具有电磁干扰屏蔽的半导体器件封装
公开(公告)号：US08022511B2
公开(公告)日：2011-09-20
申请号：US12336407
申请日：2008-12-16
申请人： Chi-Tsung Chiu , Chih-Pin Hung , Jui-Cheng Huang
发明人： Chi-Tsung Chiu , Chih-Pin Hung , Jui-Cheng Huang
IPC分类号： H01L23/552
CPC分类号： H01L24/97 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49805 , H01L23/552 , H01L24/16 , H01L24/48 , H01L24/49 , H01L2221/68331 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/16152 , H01L2924/166 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) a grounding element disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface; (4) a package body disposed adjacent to the upper surface and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a lateral surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The grounding element corresponds to a remnant of a conductive bump, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.
摘要翻译：这里描述的是具有EMI屏蔽和相关方法的半导体器件封装。在一个实施例中，半导体器件封装包括：（1）衬底单元; （2）接地元件，其设置在所述基板单元的周边附近并从所述基板单元的上表面向上延伸; （3）邻近上表面设置的半导体器件; （4）与所述上表面相邻并且覆盖所述半导体器件和所述接地元件的封装体; 和（5）邻近封装体的外表面设置并电连接到接地元件的侧表面的EMI屏蔽。封装主体的侧表面基本上与衬底单元的侧表面对准。接地元件对应于导电凸块的残余物，并且提供了入射到EMI屏蔽上的接地电磁辐射的电路径。

7. 发明申请

US20100265009A1 STACKED LC RESONATOR AND BANDPASS FILTER OF USING THE SAME 审中-公开
标题翻译：堆叠式LC谐振器和使用它的BANDPASS滤波器
公开(公告)号：US20100265009A1
公开(公告)日：2010-10-21
申请号：US12425045
申请日：2009-04-16
申请人： Tzyy-Sheng Horng , Chien-Hsun Chen , Chien-Hsiang Huang , Sung-Mao Wu , Chi-Tsung Chiu , Chih-Pin Hung
发明人： Tzyy-Sheng Horng , Chien-Hsun Chen , Chien-Hsiang Huang , Sung-Mao Wu , Chi-Tsung Chiu , Chih-Pin Hung
IPC分类号： H03H7/01 , H03H7/12
CPC分类号： H03H7/0115 , H03H2001/0085
摘要： A stacked LC resonator includes a parallel-plate capacitor, a dielectric layer and a spiral inductor. The parallel-plate capacitor has a first metal layer, a second metal layer opposed to the first metal layer and a middle dielectric layer formed between the first and second metal layers. The dielectric layer is formed on the second metal layer of the parallel-plate capacitor. The spiral inductor is formed on the dielectric layer and electrically connected with the first and second metal layers of the parallel-plate capacitor.
摘要翻译：叠层LC谐振器包括平行板电容器，电介质层和螺旋电感器。平行板电容器具有第一金属层，与第一金属层相对的第二金属层和形成在第一和第二金属层之间的中间介电层。电介质层形成在平行板电容器的第二金属层上。螺旋电感器形成在电介质层上并与平行板电容器的第一和第二金属层电连接。

8. 发明申请

US20090256244A1 SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING 有权
标题翻译：具有电磁干扰屏蔽的半导体器件封装
公开(公告)号：US20090256244A1
公开(公告)日：2009-10-15
申请号：US12489115
申请日：2009-06-22
申请人： Kuo-Hsien Liao , Chi-Tsung Chiu , Chih-Pin Hung
发明人： Kuo-Hsien Liao , Chi-Tsung Chiu , Chih-Pin Hung
IPC分类号： H01L23/552 , H01L21/56
CPC分类号： H01L23/552 , H01L21/568 , H01L21/6835 , H01L23/3121 , H01L23/49805 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2221/68345 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/81005 , H01L2224/85005 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , Y10T29/49146 , Y10T29/49153 , Y10T29/49165 , Y10T29/49789 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of an internal grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.
摘要翻译：这里描述的是具有EMI屏蔽和相关方法的半导体器件封装。在一个实施例中，半导体器件封装包括：（1）包括接地元件的衬底单元; （2）设置在所述衬底单元的上表面附近的半导体器件; （3）与基板单元的上表面相邻并且覆盖半导体器件的封装体; 和（4）EMI封装体，其与所述封装主体的外表面相邻地设置并电连接到所述接地元件的连接表面。封装主体的侧表面基本上与衬底单元的侧表面对准，并且接地元件的连接表面邻近衬底单元的侧表面电暴露。接地元件对应于内部接地通孔的残留物，并且提供了入射到EMI屏蔽层上的接地电磁辐射的电气路径。

9. 发明申请

US20060103483A1 Inductor and capacitor formed of build-up vias 有权
标题翻译：由积聚通孔形成的电感和电容器
公开(公告)号：US20060103483A1
公开(公告)日：2006-05-18
申请号：US11186859
申请日：2005-07-22
申请人： Sung-Mao Wu , Chi-Tsung Chiu , Chih-Pin Hung
发明人： Sung-Mao Wu , Chi-Tsung Chiu , Chih-Pin Hung
IPC分类号： H03H5/02
CPC分类号： H05K1/0216 , H01G4/236 , H05K1/025 , H05K1/162 , H05K1/165 , H05K2201/09509
摘要： An inductor and capacitor implemented with build-up vias. The inductor and capacitor comprise a conductor plane, a dielectric layer, an inductor/capacitor inducing build-up via and a conductor layer. There is a conducting material in the inductor/capacitor inducing build-up via and a fist end thereof is in contact with the conductor plane. The length of the inductor inducing build-up via is larger than one fourth of a signal wavelength while the length of the conductor inducing build-up via is smaller than one fourth of a signal wavelength.
摘要翻译：用积层通孔实现的电感和电容器。电感器和电容器包括导体平面，电介质层，电感器/电容器，用于引导积聚通孔和导体层。在电感器/电容器中存在导电材料，其导致积聚通孔，并且其第一端与导体平面接触。感应电感通孔的电感长度大于信号波长的四分之一，而导体积聚通孔的导体长度小于信号波长的四分之一。

10. 发明申请

US20100207259A1 SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING 有权
标题翻译：具有电磁干扰屏蔽的半导体器件封装
公开(公告)号：US20100207259A1
公开(公告)日：2010-08-19
申请号：US12770645
申请日：2010-04-29
申请人： Kuo-Hsien Liao , Jian-Cheng Chen , Chen-Chuan Fan , Chi-Tsung Chiu , Chih-Pin Hung
发明人： Kuo-Hsien Liao , Jian-Cheng Chen , Chen-Chuan Fan , Chi-Tsung Chiu , Chih-Pin Hung
IPC分类号： H01L23/552 , H01L21/78
CPC分类号： H01L23/552 , H01L21/6835 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2221/68331 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.
摘要翻译：这里描述的是具有EMI屏蔽和相关方法的半导体器件封装。在一个实施例中，半导体器件封装包括邻近衬底单元的周边设置并至少部分地在衬底单元的上表面和下表面之间延伸的接地元件。接地元件包括与衬底单元的侧表面相邻设置的凹入部分。半导体器件封装还包括EMI屏蔽，其电连接到接地元件并且与接地元件的凹入部分相邻地向内凹陷。

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