专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20090004784A1 METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE FREE OF SUBSTRATE 有权
标题翻译：用于制造无衬底的半导体封装的方法
公开(公告)号：US20090004784A1
公开(公告)日：2009-01-01
申请号：US12204066
申请日：2008-09-04
申请人： Chien-Ping Huang , Yu-Po Wang , Chih-Ming Huang
发明人： Chien-Ping Huang , Yu-Po Wang , Chih-Ming Huang
IPC分类号： H01L21/56
CPC分类号： H01L21/4832 , H01L21/4857 , H01L23/3121 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/05554 , H01L2224/05599 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/85399 , H01L2224/85439 , H01L2224/85444 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H01L2924/18161 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.
摘要翻译：提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

12. 发明申请

US20080296716A1 Sensor semiconductor device and manufacturing method thereof 审中-公开
标题翻译：传感器半导体器件及其制造方法
公开(公告)号：US20080296716A1
公开(公告)日：2008-12-04
申请号：US12151570
申请日：2008-05-07
申请人： Chang-Yueh Chan , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao , Chun-Chi Ke
发明人： Chang-Yueh Chan , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao , Chun-Chi Ke
IPC分类号： H01L21/50 , H01L23/00
CPC分类号： H01L21/56 , H01L23/3114 , H01L27/14618 , H01L27/14683 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A sensor semiconductor device and a manufacturing method thereof are disclosed. The method includes: providing a light-permeable carrier board with a plurality of metallic circuits; electrically connecting the metallic circuits to a plurality of sensor chips through conductive bumps formed on the bond pads of the sensor chips, wherein the sensor chips have been previously subjected to thinning and chip probing; filling a first dielectric layer between the sensor chips to cover the metallic circuits and peripheries of the sensor chips; forming a second dielectric layer on the sensor chips and the first dielectric layer; forming grooves between the sensor chips for exposing the metallic circuits such that a plurality of conductive traces electrically connected to the metallic circuits can be formed on the second dielectric layer; and singulating the sensor chips to form a plurality of sensor semiconductor devices. The present invention overcomes the drawbacks of breakage of trace connection due to a sharp angle formed at joints, poor electrical connection and chip damage due to an alignment error in cutting from the back of the wafer, as well as an increased cost due to multiple sputtering processes for forming traces.
摘要翻译：公开了一种传感器半导体器件及其制造方法。该方法包括：提供具有多个金属电路的透光性载板; 通过形成在传感器芯片的接合焊盘上的导电凸块将金属电路电连接到多个传感器芯片，其中传感器芯片已经预先经受了薄化和芯片探测; 在传感器芯片之间填充第一电介质层以覆盖金属电路和传感器芯片的周边; 在所述传感器芯片和所述第一介电层上形成第二电介质层; 在所述传感器芯片之间形成用于暴露所述金属电路的槽，使得可以在所述第二介电层上形成电连接到所述金属电路的多个导电迹线; 并且分离传感器芯片以形成多个传感器半导体器件。本发明克服了由于在接头处形成的尖角导致的迹线连接断裂的缺点，由于从晶片背面的切割中的对准误差导致的不良电连接和芯片损坏以及由于多次溅射而导致的成本增加形成痕迹的过程。

13. 发明申请

US20080237767A1 Sensor-type semiconductor device and manufacturing method thereof 审中-公开
标题翻译：传感器型半导体器件及其制造方法
公开(公告)号：US20080237767A1
公开(公告)日：2008-10-02
申请号：US12080002
申请日：2008-03-31
申请人： Chang-Yueh Chan , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao
发明人： Chang-Yueh Chan , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao
IPC分类号： H01L31/0203 , H01L31/18
CPC分类号： H01L27/14618 , B81C1/00888 , B81C2203/0118 , H01L23/3114 , H01L24/11 , H01L27/14683 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05548 , H01L2224/05569 , H01L2224/05644 , H01L2224/05655 , H01L2924/14 , H01L2924/00 , H01L2924/00014 , H01L2924/01074 , H01L2924/01023
摘要： A sensor-type semiconductor device and manufacturing method thereof are disclosed. The method includes providing a wafer comprising a plurality of sensor chips; forming concave grooves between the solder pads formed on the active surface of adjacent sensor chips; filling a filling material into the concave grooves and forming first conductive circuits electrically connecting the solder pads of adjacent sensor chips; mounting a light permeable body on the active surface of the wafer and thinning the non-active surface of the wafer to expose the filling material; mounting the wafer on a carrier board with second conductive circuits formed thereon corresponding in position to the filling material; forming first openings by cutting the light permeable body and the wafer to a position at which the second conductive circuits are located; forming metallic layers in the first openings by electroplating, the metallic layers electrically connecting the first and second conductive circuits of adjacent sensor chips; forming second openings by cutting the metallic layers to break the first conductive circuit connections and the second conductive circuit connections of adjacent sensor chips and meanwhile keep the first and second conductive circuits of each sensor chip still electrically connected through the metallic layers; filling a dielectric material into the second openings and removing the carrier board; and separating each of the sensor chips to form a plurality of sensor-type semiconductor devices. The invention overcomes the drawbacks of the prior art such as slanting notches formed on the non-active surface of the wafer, displacement of the notches due to the difficulty in precise alignment, as well as broken joints caused by concentrated stress generated in the slanting notches and exposed circuits.
摘要翻译：公开了一种传感器型半导体器件及其制造方法。该方法包括提供包括多个传感器芯片的晶片; 在形成在相邻传感器芯片的有效表面上的焊盘之间形成凹槽; 将填充材料填充到凹槽中并形成电连接相邻传感器芯片的焊盘的第一导电电路; 将透光体安装在晶片的活性表面上并使晶片的非活性表面变薄以暴露填充材料; 将晶片安装在载体板上，其上形成有对应于位于填充材料的第二导电电路; 通过将透光体和晶片切割到第二导电电路所在的位置来形成第一开口; 通过电镀在第一开口中形成金属层，金属层电连接相邻传感器芯片的第一和第二导电电路; 通过切割金属层来形成第二开口，以破坏相邻传感器芯片的第一导电电路连接和第二导电电路连接，同时保持每个传感器芯片的第一和第二导电电路通过金属层电连接; 将电介质材料填充到第二开口中并移除载体板; 并分离每个传感器芯片以形成多个传感器型半导体器件。本发明克服了现有技术的缺点，例如在晶片的非活性表面上形成的倾斜凹口，由于难以精确对准而导致的凹口位移以及由倾斜凹口产生的集中应力引起的断裂接头和暴露电路。

14. 发明申请

US20080230913A1 Stackable semiconductor device and fabrication method thereof 审中-公开
标题翻译：可堆叠半导体器件及其制造方法
公开(公告)号：US20080230913A1
公开(公告)日：2008-09-25
申请号：US12077223
申请日：2008-03-18
申请人： Chien-Ping Huang , Chin-Huang Chang , Chih-Ming Huang , Chun-Chi Ke
发明人： Chien-Ping Huang , Chin-Huang Chang , Chih-Ming Huang , Chun-Chi Ke
IPC分类号： H01L23/488 , H01L21/304
CPC分类号： H01L21/78 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/12 , H01L24/48 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/05001 , H01L2224/05147 , H01L2224/05155 , H01L2224/05611 , H01L2224/1147 , H01L2224/1184 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/2518 , H01L2224/48091 , H01L2224/48227 , H01L2224/81203 , H01L2224/81801 , H01L2225/06513 , H01L2225/06551 , H01L2225/06562 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2224/13099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The invention provides a stackable semiconductor device and a fabrication method thereof, including providing a wafer having a plurality of dies mounted thereon, both the die and the wafer having an active surface and a non-active surface opposing one another respectively, wherein each die has a plurality of solder pads formed on the active surface thereof and a groove formed between adjacent solder pads to form a first metal layer therein that is electrically connected to the solder pads; subsequently thinning the non-active surface of the wafer to where the grooves are located to expose the first metal layer therefrom, and forming a second metal layer on the non-active surface of the wafer for electrically connecting with the first metal layer; and separating the dies to form a plurality of stackable semiconductor devices. Thereby, the first and second metal layers formed on the active surface and the non-active surface of the semiconductor device can be stacked and connected to constitute a multi-die stack structure, thereby increasing integration without increasing the area of the stacked dies. Further, the problems known in the prior art of poor electrical connection, complicated manufacturing process and increased cost as a result of using wire bonding and TSV can be avoided.
摘要翻译：本发明提供了一种可堆叠半导体器件及其制造方法，包括提供具有安装在其上的多个管芯的晶片，晶粒和晶片两者分别具有相互相对的有源表面和非有效表面，其中每个管芯具有形成在其有效表面上的多个焊盘和形成在相邻焊盘之间的槽，以在其中形成电连接到焊盘的第一金属层; 随后使所述晶片的非活性表面变薄到所述凹槽所在的位置以暴露出所述第一金属层，以及在所述晶片的非活性表面上形成用于与所述第一金属层电连接的第二金属层; 以及分离所述管芯以形成多个可堆叠的半导体器件。由此，形成在半导体器件的有源表面和非有源表面上的第一和第二金属层可以被堆叠和连接以构成多管芯堆叠结构，从而增加集成度而不增加堆叠管芯的面积。此外，可以避免由于使用引线接合和TSV而导致的不良电连接，复杂的制造工艺和增加的成本的现有技术中已知的问题。

15. 发明授权

US07365364B2 Sensor semiconductor device with sensor chip 有权
标题翻译：传感器半导体器件与传感器芯片
公开(公告)号：US07365364B2
公开(公告)日：2008-04-29
申请号：US11162135
申请日：2005-08-30
申请人： Chien-Ping Huang , Chih-Ming Huang , Cheng-Yi Chang
发明人： Chien-Ping Huang , Chih-Ming Huang , Cheng-Yi Chang
IPC分类号： H01L29/267 , H01L29/22
CPC分类号： H01L27/14683 , H01L27/14618 , H01L2224/24226
摘要： A sensor semiconductor device and a method for fabricating the same are proposed. A sensor chip is mounted on a substrate, and a dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the substrate and the sensor chip. The dielectric layer is formed with an opening for exposing a sensor region of the sensor chip. A light-penetrable lid covers the opening of the dielectric layer, such that light is able to penetrate the light-penetrable lid to reach the sensor region and activate the sensor chip. The sensor chip can be electrically connected to an external device via a plurality of solder balls implanted on a surface of the substrate not for mounting the sensor chip. Therefore, the sensor semiconductor device is fabricated in a cost-effective manner, and circuit cracking and a know good die (KGD) problem are prevented.
摘要翻译：提出了一种传感器半导体器件及其制造方法。传感器芯片安装在基板上，并且在基板上形成电介质层和电路层，其中电路层电连接到基板和传感器芯片。电介质层形成有用于暴露传感器芯片的传感器区域的开口。透光盖子覆盖电介质层的开口，使得光线能够穿透透光盖子到达传感器区域并激活传感器芯片。传感器芯片可以通过植入在基板的表面上的多个焊球电连接到外部设备，而不用于安装传感器芯片。因此，传感器半导体器件以成本有效的方式制造，并且防止了电路破裂和知道的裸芯片（KGD）问题。

16. 发明授权

US07354796B2 Method for fabricating semiconductor package free of substrate 有权
标题翻译：制造不含衬底的半导体封装的方法
公开(公告)号：US07354796B2
公开(公告)日：2008-04-08
申请号：US11821269
申请日：2007-06-22
申请人： Chien-Ping Huang , Yu-Po Wang , Chih-Ming Huang
发明人： Chien-Ping Huang , Yu-Po Wang , Chih-Ming Huang
IPC分类号： H01L21/00
CPC分类号： H01L21/4857 , H01L21/4832 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/142 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/4985 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/85 , H01L24/97 , H01L2221/68345 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49171 , H01L2224/81801 , H01L2224/85001 , H01L2224/85439 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/18165 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.
摘要翻译：提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

17. 发明授权

US07342318B2 Semiconductor package free of substrate and fabrication method thereof 有权
标题翻译：不含衬底的半导体封装及其制造方法
公开(公告)号：US07342318B2
公开(公告)日：2008-03-11
申请号：US11112145
申请日：2005-04-21
申请人： Chien Ping Huang , Yu-Po Wang , Chih-Ming Huang
发明人： Chien Ping Huang , Yu-Po Wang , Chih-Ming Huang
IPC分类号： H01L29/40
CPC分类号： H01L21/4857 , H01L21/4832 , H01L21/561 , H01L21/568 , H01L23/3121 , H01L23/58 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2221/68345 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H05K3/007 , H05K3/3457 , H05K3/4682 , H05K2203/0152 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.
摘要翻译：提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

18. 发明申请

US20070278701A1 Semiconductor package and method for fabricating the same 审中-公开
标题翻译：半导体封装及其制造方法
公开(公告)号：US20070278701A1
公开(公告)日：2007-12-06
申请号：US11591800
申请日：2006-11-01
申请人： Cheng-Yi Chang , Chien-Ping Huang , Chih-Ming Huang , Chieh-Yuan Lin , Cheng-Hsu Hsiao
发明人： Cheng-Yi Chang , Chien-Ping Huang , Chih-Ming Huang , Chieh-Yuan Lin , Cheng-Hsu Hsiao
IPC分类号： H01L23/28
CPC分类号： H01L21/561 , H01L21/481 , H01L23/3121 , H01L23/49805 , H01L23/49811 , H01L24/48 , H01L24/97 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H01L2224/85 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a method for fabricating the same are disclosed. The method includes installing a plurality of conductive components on a plurality of chip carriers of a chip carrier module, connecting electrically the conductive components to electrical connection points of the adjacent chip carriers, mounting and electrically connecting a semiconductor chip to each of the chip carries, forming an encapsulant for enveloping the semiconductor chip and the conductive components, cutting the chip carriers to separate the conductive components installed thereon, exposing a portion of the conductive components out of the encapsulant, forming on the exposed portion of the conductive components an electroplated layer of nickel/gold, and separating the chip carriers from each other. The conductive components exposed out of the encapsulant provide extra electrical connection points and thereby promote the functionalities of electronic products.
摘要翻译：公开了一种半导体封装及其制造方法。该方法包括在芯片载体模块的多个芯片载体上安装多个导电组件，将导电组件电连接到相邻芯片载体的电连接点，将半导体芯片安装并电连接到每个芯片载体，形成用于包封半导体芯片和导电部件的密封剂，切割芯片载体以分离安装在其上的导电组件，将一部分导电组分暴露于密封剂外，在导电组件的暴露部分上形成电镀层镍/金，并且将芯片载体彼此分离。从密封剂露出的导电组件提供额外的电连接点，从而促进电子产品的功能。

19. 发明申请

US20070249101A1 Method for fabricating semiconductor package free of substrate 有权
标题翻译：制造不含衬底的半导体封装的方法
公开(公告)号：US20070249101A1
公开(公告)日：2007-10-25
申请号：US11821269
申请日：2007-06-22
申请人： Chien Huang , Yu-Po Wang , Chih-Ming Huang
发明人： Chien Huang , Yu-Po Wang , Chih-Ming Huang
IPC分类号： H01L21/60
CPC分类号： H01L21/4857 , H01L21/4832 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/142 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/4985 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/85 , H01L24/97 , H01L2221/68345 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49171 , H01L2224/81801 , H01L2224/85001 , H01L2224/85439 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/18165 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.
摘要翻译：提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

20. 发明申请

US20070164084A1 Electronic carrier board 有权
标题翻译：电子载板
公开(公告)号：US20070164084A1
公开(公告)日：2007-07-19
申请号：US11654273
申请日：2007-01-16
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Wen-Tsung Tseng , Chih-Ming Huang
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Wen-Tsung Tseng , Chih-Ming Huang
IPC分类号： A47J36/02
CPC分类号： H01R43/0256 , H01R43/0228 , H05K3/3442 , H05K3/3452 , H05K2201/0989 , H05K2201/099 , H05K2201/10636 , Y02P70/611 , Y02P70/613
摘要： An electronic carrier board is provided, including a carrier, at least two paired bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings corresponding in position to the two bond pads. The openings are aligned in the same direction and expose at least a first sidewall and a second sidewall of each of the two bond pads. The first sidewall is perpendicular to an alignment direction of the bond pads and the second sidewall is parallel to the alignment direction of the bond pads. A distance between the first sidewall of at least one of the bond pads and a corresponding side of a corresponding one of the openings is at least about 50 μm greater than a distance between the second sidewall of the at least one bond pad and a corresponding side of the corresponding opening.
摘要翻译：提供一种电子载体板，包括载体，形成在载体上的至少两个成对的接合焊盘和覆盖载体的保护层。保护层形成有与两个接合焊盘相对应的开口。开口沿相同方向排列，并暴露两个接合焊盘中的每一个的至少第一侧壁和第二侧壁。第一侧壁垂直于接合焊盘的对准方向，第二侧壁平行于接合焊盘的对准方向。至少一个接合焊盘的第一侧壁和对应的一个开口的对应侧之间的距离比至少一个接合焊盘的第二侧壁和相应侧面之间的距离大至少约50μm 的相应开口。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式