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11. 发明申请

US20100039152A1 METHOD AND APPARATUS FOR ADAPTIVE CLOCK PHASE CONTROL FOR LSI POWER REDUCTION 有权
标题翻译：用于LSI功率降低的适应时钟相位控制的方法和装置
公开(公告)号：US20100039152A1
公开(公告)日：2010-02-18
申请号：US12192385
申请日：2008-08-15
申请人： Chiaki Takano
发明人： Chiaki Takano
IPC分类号： H03K5/13
CPC分类号： H03K5/13 , H03K5/1506 , H03K2005/00039 , H03K2005/0013
摘要： Methods and apparatus for distributing a clock signal to a digital circuit provide for: producing a clock signal; and delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.
摘要翻译：用于将时钟信号分配给数字电路的方法和装置提供：产生时钟信号; 并且延迟，提前或者使时钟信号不变以产生作为控制信号的函数的输出时钟信号，其中时钟信号和输出时钟信号之间的延迟或提前量（相位差）是时间的函数变化到数字电路的电源电压的大小。

12. 发明申请

US20090201055A1 Methods and Apparatus For Managing LSI Power Consumption and Degradation Using Clock Signal Conditioning 有权
标题翻译：使用时钟信号调理管理LSI功耗和降级的方法和装置
公开(公告)号：US20090201055A1
公开(公告)日：2009-08-13
申请号：US12029764
申请日：2008-02-12
申请人： Chiaki Takano
发明人： Chiaki Takano
IPC分类号： H03B19/00
CPC分类号： H03K19/0016
摘要： Methods and apparatus for distributing clock signals to an integrated circuit provide for: producing, in a slow mode of operation, a first clock signal having at least first and second on-pulses of differing first and second on-times each period, respectively, where a sum of the first and second on-times is approximately equal to a sum of off-times each period; distributing the first clock signal through a distribution tree and terminating at a plurality of final buffer circuits that produce respective distributed clock signals from which respective second clock signals are produced to supply at least a portion of the integrated circuit; deleting the second on-pulse from each of the distributed clock signals each period to produce the respective second clock signals, the second clock signals each including at least a portion of the first on-pulse, but none of the second on-pulse each period.
摘要翻译：用于将时钟信号分配到集成电路的方法和装置提供：在慢速操作模式下产生具有分别具有不同的第一和第二接通时间的每个周期的至少第一和第二导通脉冲的第一时钟信号，其中，第一和第二接通时间的总和近似等于每个周期的关闭时间的总和; 通过分配树分配第一时钟信号并终止于产生各自的分布式时钟信号的多个最终缓冲器电路，从其产生相应的第二时钟信号以提供集成电路的至少一部分; 从每个周期的每个分布式时钟信号中删除第二导通脉冲以产生相应的第二时钟信号，所述第二时钟信号各自包括第一接通脉冲的至少一部分，但是每个周期中没有第二导通脉冲。

13. 发明申请

US20070146037A1 METHODS AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A PROCESSOR USING CLOCK SIGNAL CONTROL 有权
标题翻译：使用时钟信号控制在处理器中降低功耗的方法和装置
公开(公告)号：US20070146037A1
公开(公告)日：2007-06-28
申请号：US11318228
申请日：2005-12-22
申请人： Chiaki Takano , Daniel Stasiak , Nathan Chelstrom , Steven Ferguson
发明人： Chiaki Takano , Daniel Stasiak , Nathan Chelstrom , Steven Ferguson
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/126 , Y02D10/128
摘要： Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.
摘要翻译：方法和装置提供：产生指示睡眠模式的第一基本上稳定的状态逻辑电平的控制信号，以及指示正常模式的第二基本稳定的逻辑电平; 当控制信号处于第一逻辑电平时产生处于基本稳态零电平的门信号，并且当控制信号处于第二逻辑电平时以当地时钟频率振荡; 根据门信号从系统时钟信号产生本地时钟信号; 并且在控制信号的原点与产生栅极信号的位置之间插入至少一个信号传播锁存电路。

14. 发明申请

US20070063756A1 Methods and apparatus for managing clock skew 有权
公开(公告)号：US20070063756A1
公开(公告)日：2007-03-22
申请号：US11233423
申请日：2005-09-22
申请人： Chiaki Takano , Stephen Weitzel
发明人： Chiaki Takano , Stephen Weitzel
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal, provide a second signal having a second frequency, synchronize the second signal with the first signal, and propagate the synchronized second signal to at least one other clock mesh of the apparatus.

15. 发明授权

US5374862A Super buffer and DCFL circuits with Schottky barrier diode 失效
标题翻译：超缓冲器和具有肖特基势垒二极管的DCFL电路
公开(公告)号：US5374862A
公开(公告)日：1994-12-20
申请号：US19440
申请日：1993-02-18
申请人： Chiaki Takano
发明人： Chiaki Takano
IPC分类号： H01L21/8234 , H01L27/06 , H03K19/017 , H03K19/0952 , H03K19/094
CPC分类号： H01L27/0605 , H03K19/0952
摘要： In a GaAs IC using an E/R type DCFL circuit or E/D type DCFL circuit, a Schottky barrier diode is connected between the positive polarity power source of the DCFL circuit and a load element. A deterioration of switching speed is prevented even in case of using a power source voltage of 2 V in the GaAs IC. Addition of the Schottky barrier diode in a super buffer circuit to prevent a slow increase in output voltage in the circuit is also disclosed.
摘要翻译：在使用E / R型DCFL电路或E / D型DCFL电路的GaAs IC中，肖特基势垒二极管连接在DCFL电路的正极性电源和负载元件之间。即使在GaAs IC中使用2V的电源电压的情况下也防止开关速度的劣化。还公开了在超缓冲电路中添加肖特基势垒二极管以防止电路中输出电压的缓慢增加。

16. 发明授权

US07676683B2 Method and system for rebooting a processor in a multi-processor system 失效
标题翻译：在多处理器系统中重新启动处理器的方法和系统
公开(公告)号：US07676683B2
公开(公告)日：2010-03-09
申请号：US11509493
申请日：2006-08-24
申请人： Atsushi Tsuji , Chiaki Takano , Atsuo Mangyo , Masaaki Nozaki , Shunsaku Tokito , Hiroaki Terakawa
发明人： Atsushi Tsuji , Chiaki Takano , Atsuo Mangyo , Masaaki Nozaki , Shunsaku Tokito , Hiroaki Terakawa
IPC分类号： G06F1/00 , G06F9/00 , G06F13/00 , G06F12/00
CPC分类号： G06F9/4418
摘要： Processors arranged in a multi-processor configuration for substantially parallel operations receive their initialization data in order to start operations, such as graphics computations, real-time multimedia streaming, etc. Due to a change in the processing load, one or more processors might be deactivated. Subsequently, the load increases to such a level that requires all or some of the deactivated processors to be active again. In this case, the boot-up process of the entire system is not carried out as it would be time-consuming and wasteful; instead, responsive to a control signal only those processors that were previously in inactive mode are re-initialized by selecting a configuration data supplied by another processor, controller or any other intelligent programmable device. Alternatively, the configuration data may be accessed and retrieved from a local storage medium individually located in each processor, thereby re-booting only those inactive processors and without re-initializing the entire system.
摘要翻译：以多处理器配置布置的用于基本并行操作的处理器接收它们的初始化数据，以便开始诸如图形计算，实时多媒体流等操作。由于处理负载的变化，一个或多个处理器可能是停用随后，负载增加到要求全部或一些停用处理器再次活动的水平。在这种情况下，整个系统的启动过程不会执行，因为这将是耗时且浪费的; 相反，响应于控制信号，仅通过选择由另一个处理器，控制器或任何其他智能可编程设备提供的配置数据来重新初始化先前处于非活动模式的处理器。或者，可以从单独位于每个处理器中的本地存储介质访问和检索配置数据，从而仅重新引导那些不活动的处理器，并且不重新初始化整个系统。

17. 发明授权

US07233188B1 Methods and apparatus for reducing power consumption in a processor using clock signal control 有权
标题翻译：使用时钟信号控制来降低处理器功耗的方法和装置
公开(公告)号：US07233188B1
公开(公告)日：2007-06-19
申请号：US11318228
申请日：2005-12-22
申请人： Chiaki Takano , Daniel Lawrence Stasiak , Nathan Paul Chelstrom , Steven Ross Ferguson
发明人： Chiaki Takano , Daniel Lawrence Stasiak , Nathan Paul Chelstrom , Steven Ross Ferguson
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/126 , Y02D10/128
摘要： Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.
摘要翻译：方法和装置提供：产生指示睡眠模式的第一基本上稳定的状态逻辑电平的控制信号，以及指示正常模式的第二基本稳定的逻辑电平; 当控制信号处于第一逻辑电平时产生处于基本稳态零电平的门信号，并且当控制信号处于第二逻辑电平时以当地时钟频率振荡; 根据门信号从系统时钟信号产生本地时钟信号; 并且在控制信号的原点与产生栅极信号的位置之间插入至少一个信号传播锁存电路。

18. 发明申请

US20070011531A1 Methods and apparatus for managing clock skew between clock domain boundaries 有权
标题翻译：用于管理时钟域边界之间的时钟偏移的方法和装置
公开(公告)号：US20070011531A1
公开(公告)日：2007-01-11
申请号：US11149103
申请日：2005-06-09
申请人： Chiaki Takano
发明人： Chiaki Takano
IPC分类号： G01R31/28
CPC分类号： G01R31/31727 , G01R31/31726
摘要： Methods and apparatus provide for: a plurality of stages of combinational logic, each stage including a full latch circuit operable to transfer data into the given stage of combinational logic and a transparent latch circuit operable transfer output data from the given stage of combinational logic to a next of the stages; in each stage, passing state changes of output data from the given combinational logic irrespective of when such changes occur when a clock signal of the transparent latch circuit is at a first of two logic levels; and in each stage, withholding state changes of the output data until the clock signal of the transparent latch circuit transitions from the second of the two logic levels to the first logic level.
摘要翻译：方法和装置提供：多级的组合逻辑，每级包括可操作以将数据传送到组合逻辑的给定级的完全锁存电路和透明锁存电路，可操作地将组合逻辑的给定阶段的输出数据传送到接下来的阶段; 无论在透明锁存电路的时钟信号是否处于两个逻辑电平中的第一个时，何时发生这种变化，在每个阶段都将来自给定组合逻辑的输出数据的状态变化通过; 并且在每个阶段中，直到透明锁存电路的时钟信号从两个逻辑电平中的第二逻辑电平转换到第一逻辑电平为止，输出数据保持状态变化。

19. 发明授权

US06201269B1 Junction field effect transistor and method of producing the same 失效
标题翻译：结场效应晶体管及其制造方法
公开(公告)号：US06201269B1
公开(公告)日：2001-03-13
申请号：US08458724
申请日：1995-06-02
申请人： Chiaki Takano , Hidetoshi Kawasaki , Masaru Wada
发明人： Chiaki Takano , Hidetoshi Kawasaki , Masaru Wada
IPC分类号： H01L2976
CPC分类号： H01L29/66924 , H01L21/8252 , H01L27/0605 , H01L27/0629 , H01L29/0649 , H01L29/1066 , H01L29/808
摘要： For suppressing generation of leakage current and side-gate effect in a junction field effect transistor, a gate extension is formed on a semi-insulative compound semiconductor substrate in a manner to extend from a gate and to protrude outward beyond a channel transversely thereto, and an insulating layer is formed on the semi-insulative compound semiconductor substrate under the gate extension. A method of producing this transistor comprises the steps of first forming a channel and a source-drain on a substrate, then forming a gate on the channel together with a gate extension which extends from the gate and protrudes outward beyond the channel transversely thereto, and forming an insulating layer adjacently to the channel and the source-drain in such a manner that no gap is existent between the insulating layer and at least the channel.
摘要翻译：为了抑制结型场效应晶体管中的漏电流和侧栅效应的产生，在半绝缘化合物半导体基板上以从栅极延伸并向外突出超过横向通道的方式形成栅极延伸，以及在栅极延伸部分的半绝缘性化合物半导体基板上形成绝缘层。制造该晶体管的方法包括以下步骤：首先在衬底上形成沟道和源极 - 漏极，然后在沟道上形成栅极以及从栅极延伸并从其横向向外突出超过沟槽的栅极延伸，以及以与绝缘层和至少沟道之间不存在间隙的方式形成与沟道和源极 - 漏极相邻的绝缘层。

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