专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5734847A Method and apparatus for enabling intelligent I/O subsystems using PCI I/O devices 失效
标题翻译：使用PCI I / O设备实现智能I / O子系统的方法和装置
公开(公告)号：US5734847A
公开(公告)日：1998-03-31
申请号：US490775
申请日：1995-06-15
申请人： Elliott Garbus , Barry Davis
发明人： Elliott Garbus , Barry Davis
IPC分类号： G06F13/40 , G06F13/38
CPC分类号： G06F13/404 , G06F13/4027
摘要： A processor for creating an intelligent input/output subsystems which includes a local processor coupled to a local system bus; a local memory controller coupled to the local system bus that enables access to a memory from the local system bus; a bus bridge having a first bus interface coupled to a first component bus; a second bus interface coupled to a second component bus, the bus bridge including means for creating an address space which is private to the secondary component bus such that the bridge will not send any address found in the private address space upstream to the primary component bus; and address translation means coupled to the local system bus and the bus bridge for translating addresses between the local system bus and the second component bus. A method for creating private devices comprising the steps of configuring the bus bridge to disable the assertion by the first component of a component select signal on the second component bus; creating an address space which is private to the secondary component bus such that the bridge will not send any address found in the private address space upstream to the primary component bus; translating the private address to a local system address in a local system address space; and translating a local system address contained in the local system address space to the private address.
摘要翻译：一种用于创建智能输入/输出子系统的处理器，其包括耦合到本地系统总线的本地处理器; 耦合到本地系统总线的本地存储器控制器，其使得能够从本地系统总线访问存储器; 具有耦合到第一组件总线的第一总线接口的总线桥; 耦合到第二组件总线的第二总线接口，所述总线桥接器包括用于创建对所述次要组件总线是专用的地址空间的装置，使得所述桥接器将不发送在所述主组件总线上游的专用地址空间中发现的任何地址 ; 以及耦合到本地系统总线和总线桥的地址转换装置，用于翻译本地系统总线和第二组件总线之间的地址。一种用于创建专用设备的方法，包括以下步骤：配置所述总线桥以禁止所述第一分量对所述第二组件总线上的分量选择信号的所述断言; 创建对次要组件总线是专用的地址空间，使得该桥接器将不会向主分量总线上游发送专用地址空间中发现的任何地址; 将私有地址转换为本地系统地址空间中的本地系统地址; 并将本地系统地址空间中包含的本地系统地址转换为私有地址。

12. 发明授权

US6128718A Apparatus and method for a base address register on a computer peripheral device supporting configuration and testing of address space size 失效
标题翻译：支持配置和测试地址空间大小的计算机外围设备上的基地址寄存器的装置和方法
公开(公告)号：US6128718A
公开(公告)日：2000-10-03
申请号：US919376
申请日：1997-08-28
申请人： Mark A. Schmisseur , Barry Davis
发明人： Mark A. Schmisseur , Barry Davis
IPC分类号： G06F9/30 , G06F9/355 , G06F9/35 , G06F12/10
CPC分类号： G06F9/342
摘要： A method for providing a base address register in a computer system that allows the length of the base address portion of an address to be changed and thereby allows various sizes of address spaces to be supported by the same base address register. The method employs steps that enable and disable bits of the base address register to properly support the desired address space size. Some embodiments of the method set disabled bits of the base address register to a known value. An apparatus that employs the method includes a second register connected to the base address register to supply signals that enable and disable bits of the base address register appropriately.
摘要翻译：一种用于在计算机系统中提供基地址寄存器的方法，其允许改变地址的基址部分的长度，从而允许相同基址寄存器支持各种大小的地址空间。该方法采用启用和禁用基地址寄存器的位以适当地支持所需地址空间大小的步骤。该方法的一些实施例将基址寄存器的禁用位设置为已知值。采用该方法的装置包括连接到基地址寄存器的第二寄存器，以适当地提供启用和禁用基地址寄存器的位的信号。

13. 发明授权

US5903773A System to improve trapping of I/O instructions in a peripheral component interconnect bus computer system and method therefor 失效
标题翻译：用于改善外围组件互连总线计算机系统中的I / O指令的捕获的系统及其方法
公开(公告)号：US5903773A
公开(公告)日：1999-05-11
申请号：US704281
申请日：1996-08-28
申请人： Nicholas Julian Richardson , Barry Davis , Gary Hicok
发明人： Nicholas Julian Richardson , Barry Davis , Gary Hicok
IPC分类号： G06F11/07 , G06F11/30
CPC分类号： G06F11/0745 , G06F11/0793
摘要： A system for trapping I/O instructions. The system is comprised of at least one peripheral controller for receiving a plurality of I/O instructions and for initiating trapping of an un-executable I/O instruction by issuing a target abort signal when the peripheral controller senses a power off condition in a peripheral device. A system controller is coupled to the at least one peripheral controller for receiving the target abort signal from the at least one peripheral controller and for sequentially: issuing a system management interrupt (SMI) signal; counting a predetermined time period to allow recognition of the SMI signal; and issuing a cycle completion signal after counting the predetermined time period. A CPU is coupled to the system controller for issuing a plurality of I/O instructions and for receiving the SMI signal and the cycle completion signal from the system controller.
摘要翻译：用于捕获I / O指令的系统。该系统包括至少一个外围控制器，用于接收多个I / O指令，并且用于当外设控制器感测到外围设备的电源关闭状态时，通过发出目标中止信号来开始捕获不可执行的I / O指令设备。系统控制器耦合到所述至少一个外围控制器，用于从所述至少一个外围控制器接收目标中止信号，并且用于顺序地：发出系统管理中断（SMI）信号; 计数预定时间段以允许SMI信号的识别; 以及在计数所述预定时间段之后发出循环完成信号。 CPU耦合到系统控制器，用于发出多个I / O指令，并用于从系统控制器接收SMI信号和循环完成信号。

14. 发明申请

US20050145089A1 Handi-guitar (for the handicapped guitar player) 有权
标题翻译：手吉他（用于残疾吉他手）
公开(公告)号：US20050145089A1
公开(公告)日：2005-07-07
申请号：US10916575
申请日：2004-08-12
申请人： Barry Davis
发明人： Barry Davis
IPC分类号： G10D3/00 , G10D3/08 , G10H5/00 , H04Q1/18
CPC分类号： G10D3/08
摘要： A thin flat body of clear plastic with a key pad (20) on the inside back base (12), and a chord scale (22) on the outside front of the base (10). The chord scale is fitted with braille nodules (24) for guiding the proper placement of the fingers on the EZ chord. On the bottom or lower side of the base (10) (12) is a gripping angle (14) for the learning chord device. On the top or upper side, and bottom or lower side of the base (10) (12) are gripping angles (14) (16) for the universal chord device. One EZ chord is a device that when manipulated by a human hand, or an artificial hand, is pressed and positioned onto the guitar neck, fret and strings to form and sound guitar chords and/or notes. The EZ chord devices can be used by mentally, physically, or visually handicapped people as well as non-handicapped people, to play and/or learn to play the guitar.
摘要翻译：一个透明塑料薄扁平体，内侧背部底座（12）上带有一个键盘（20），和一个在底座（10）的外侧前方的弦标（22）。弦标配有盲文结节（24），用于将手指正确放置在EZ弦上。在基座（10）（12）的底部或底侧上是用于学习弦装置的夹紧角（14）。在基座（10）（12）的顶部或上侧以及底侧或下侧是用于通用和弦装置的夹紧角（14）（16）。一个EZ和弦是一种装置，当用人的手或人造手操纵时，被按压并放置在吉他颈部上，装置和琴弦以形成吉他和弦和/或音符。 EZ和弦设备可以被智力，身体或视觉残疾人以及非残疾人使用，以播放和/或学习弹吉他。

15. 发明授权

US06353794B1 Air travel information and computer data compilation, retrieval and display method and system 有权
标题翻译：航空旅行信息和计算机数据汇编，检索和显示方法及系统
公开(公告)号：US06353794B1
公开(公告)日：2002-03-05
申请号：US09421167
申请日：1999-10-19
申请人： Barry Davis , Scott Blachowicz , Larry Brasfield , Dennis Howard , David Helms , Craig Paynter , Randy Robertson , James Rouse
发明人： Barry Davis , Scott Blachowicz , Larry Brasfield , Dennis Howard , David Helms , Craig Paynter , Randy Robertson , James Rouse
IPC分类号： G01C2100
CPC分类号： G08G5/0043 , G01C21/00 , G01C23/00 , G08G5/0095
摘要： A system, method, and computer program for managing integrated real-time information about air flight trips and providing that information to multiple users by way of a flight operations system (FOS), including a data engine (DE) and render engine (RE). A computerized Upstream Distribution Center (UDC) containing a packet manager connects to the FOS and to a user interface including a computer display using text, image and color. The UDC is connectable to multiple user interfaces containing copies of the computer program through computer networks by which information is collected and propagated on a real time basis using object-relational mapping, object caching and proactive notification or “push” technology.
摘要翻译：一种用于管理关于航空飞行旅行的综合实时信息并通过飞行操作系统（FOS）向多个用户提供信息的系统，方法和计算机程序，包括数据引擎（DE）和渲染引擎（RE）。包含分组管理器的计算机上行分发中心（UDC）连接到FOS，并连接到包括使用文本，图像和颜色的计算机显示器的用户界面。 UDC可通过计算机网络连接到包含计算机程序副本的多个用户界面，通过该网络，使用对象关系映射，对象缓存和主动通知或“推送”技术实时地收集和传播信息。

16. 发明授权

US5859987A Method and apparatus for providing multiple configuration reset modes for an intelligent bridge 失效
标题翻译：为智能桥提供多种配置复位模式的方法和装置
公开(公告)号：US5859987A
公开(公告)日：1999-01-12
申请号：US536156
申请日：1995-09-29
申请人： Byron Gillespie , Barry Davis
发明人： Byron Gillespie , Barry Davis
IPC分类号： G06F13/40
CPC分类号： G06F13/4027
摘要： An integrated circuit for providing multiple configuration modes in a multi-funtion intelligent bridge that includes an integrated processor. A first circuit, coupled to a first external bus, for selectively generating retry cycles onto the first external bus in response to a retry signal is provided. A second circuit, coupled to a local processor, for selectively resetting a local processor that is integrated in the intelligent bridge in response to a reset signal is provided. The first and second circuit, in conjunction with the retry signal and the reset signal, selectively provides one of a multiple number of configuration reset modes for the multi-function intelligent bridge.
摘要翻译：一种用于在包括集成处理器的多功能智能桥中提供多种配置模式的集成电路。提供耦合到第一外部总线的第一电路，用于响应于重试信号选择性地产生到第一外部总线上的重试周期。提供了耦合到本地处理器的第二电路，用于响应于复位信号选择性地复位集成在智能桥中的本地处理器。第一和第二电路结合重试信号和复位信号，选择性地为多功能智能桥提供多种配置复位模式之一。

17. 发明授权

US5848249A Method and apparatus for enabling intelligent I/O subsystems using PCI I/O devices 失效
标题翻译：使用PCI I / O设备实现智能I / O子系统的方法和装置
公开(公告)号：US5848249A
公开(公告)日：1998-12-08
申请号：US893413
申请日：1997-07-11
申请人： Elliott Garbus , Barry Davis
发明人： Elliott Garbus , Barry Davis
IPC分类号： G06F13/40 , G06F13/38
CPC分类号： G06F13/404 , G06F13/4027
摘要： An apparatus having a first interface for coupling to a first component bus; a second interface for coupling to a second component bus; an address translation unit coupled to the second interface; and a bus bridge coupled to the first interface and to the second interface. The bus bridge has a first configuration register for disabling an assertion by a first component coupled to the first interface of a component select signal on said second interface; a second configuration register for disabling a propagation by the bus bridge of a private address, contained in an address space which is private to the second interface, from the second interface to the first interface, and to disable a response by the bus bridge to the private address sent from the first interface; and a third configuration register in the address translation unit such that the address translation unit will translate the private address to a local system address in a local system address space, and also translate a local system address contained in the local system address space to the private address.
摘要翻译：一种具有用于耦合到第一分量总线的第一接口的装置; 用于耦合到第二组件总线的第二接口; 耦合到所述第二接口的地址转换单元; 以及耦合到第一接口和第二接口的总线桥。总线桥具有第一配置寄存器，用于禁用由所述第二接口上的组件选择信号耦合到第一接口的第一组件的断言; 第二配置寄存器，用于禁止由第二接口到第一接口的包含在第二接口的私有地址空间中的专用地址的总线桥传播，并且禁止总线桥接到第一接口的响应从第一个接口发送的私有地址; 以及地址转换单元中的第三配置寄存器，使得地址转换单元将私有地址转换为本地系统地址空间中的本地系统地址，并将本地系统地址空间中包含的本地系统地址转换为私有地址空间地址。

18. 发明授权

US3994912A 1-Oxides of Schiff bases of 6-aminopenicillanic acid 失效
标题翻译： 1-氨基青霉烷酸的席夫碱1-氧化物
公开(公告)号：US3994912A
公开(公告)日：1976-11-30
申请号：US454531
申请日：1974-03-25
申请人： Douglas Barry Davis , Ekkehard Bohme , Joseph Edward Dolfini
发明人： Douglas Barry Davis , Ekkehard Bohme , Joseph Edward Dolfini
IPC分类号： C07D499/42 , C07D499/02
CPC分类号： C07D499/42
摘要： Compounds containing a cephem nucleus are prepared by heating a 1-oxide of a Schiff base of 6-aminopenicillanic acid. These cephem compounds are useful as intermediates in the preparation of physiologically active cephalosporins.
摘要翻译：含有头孢烯核的化合物通过加热6-氨基青霉烷酸的席夫碱的1-氧化物来制备。这些头孢烯化合物可用作制备生理活性头孢菌素的中间体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式