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1. 发明授权

US6128718A Apparatus and method for a base address register on a computer peripheral device supporting configuration and testing of address space size 失效
标题翻译：支持配置和测试地址空间大小的计算机外围设备上的基地址寄存器的装置和方法
公开(公告)号：US6128718A
公开(公告)日：2000-10-03
申请号：US919376
申请日：1997-08-28
申请人： Mark A. Schmisseur , Barry Davis
发明人： Mark A. Schmisseur , Barry Davis
IPC分类号： G06F9/30 , G06F9/355 , G06F9/35 , G06F12/10
CPC分类号： G06F9/342
摘要： A method for providing a base address register in a computer system that allows the length of the base address portion of an address to be changed and thereby allows various sizes of address spaces to be supported by the same base address register. The method employs steps that enable and disable bits of the base address register to properly support the desired address space size. Some embodiments of the method set disabled bits of the base address register to a known value. An apparatus that employs the method includes a second register connected to the base address register to supply signals that enable and disable bits of the base address register appropriately.
摘要翻译：一种用于在计算机系统中提供基地址寄存器的方法，其允许改变地址的基址部分的长度，从而允许相同基址寄存器支持各种大小的地址空间。该方法采用启用和禁用基地址寄存器的位以适当地支持所需地址空间大小的步骤。该方法的一些实施例将基址寄存器的禁用位设置为已知值。采用该方法的装置包括连接到基地址寄存器的第二寄存器，以适当地提供启用和禁用基地址寄存器的位的信号。

2. 发明授权

US06173344B2 SCSI bus transceiver and method for making the same 失效
标题翻译： SCSI总线收发器及其制作方法
公开(公告)号：US06173344B2
公开(公告)日：2001-01-09
申请号：US09085671
申请日：1998-05-27
申请人： Abdul Waheed Mohammed , Peter K. Cheung , Barry Davis , Christopher Burns
发明人： Abdul Waheed Mohammed , Peter K. Cheung , Barry Davis , Christopher Burns
IPC分类号： G06F1300
CPC分类号： G06F13/4072
摘要： Disclosed is a SCSI host adapter for use in a computer system. The SCSI host adapter is configured to provide the computer system with interconnection with internal and/or external target devices. The SCSI host adapter includes a low voltage differential connector for interconnecting to a low voltage differential bus, and the low voltage differential bus is configured to communicate a first transaction. The SCSI host adapter also includes a single ended connector for interconnecting to a single ended bus, and the single ended bus is configured to communicate a second transaction. Furthermore, the SCSI host adapter includes a transceiver unit that is configured to interface between the low voltage differential bus and the single ended bus and produce a target information signal. The target information signal is configured to indicate whether the first transaction or the second transaction is occurring between the SCSI host adapter and the low voltage differential bus or the single ended bus.
摘要翻译：公开了一种用于计算机系统的SCSI主机适配器。 SCSI主机适配器被配置为向计算机系统提供与内部和/或外部目标设备的互连。 SCSI主机适配器包括用于互连到低电压差分总线的低压差分连接器，并且低电压差分总线被配置为传送第一事务。 SCSI主机适配器还包括用于互连到单端总线的单端连接器，并且单端总线被配置为传送第二事务。此外，SCSI主机适配器包括收发器单元，其被配置为在低电压差分总线和单端总线之间进行接口并产生目标信息信号。目标信息信号被配置为指示在SCSI主机适配器和低电压差分总线或单端总线之间是否发生第一事务或第二事务。

3. 发明授权

US5793992A Method and apparatus for arbitrating access to main memory of a computer system 失效
标题翻译：用于仲裁访问计算机系统的主存储器的方法和装置
公开(公告)号：US5793992A
公开(公告)日：1998-08-11
申请号：US664107
申请日：1996-06-13
申请人： James C. Steele , Barry Davis , Philip Wszolek , Brian Fall , Swaroop Adusumilli , David Cassetti , Rodney Pesavento , Nick Richardson
发明人： James C. Steele , Barry Davis , Philip Wszolek , Brian Fall , Swaroop Adusumilli , David Cassetti , Rodney Pesavento , Nick Richardson
IPC分类号： G06F13/16 , G06F13/40 , G06F13/00 , G06F13/362
CPC分类号： G06F13/1605 , G06F13/4027 , G06F13/4031
摘要： A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with peripheral devices, and because the internal bus is occasionally freed up during the data transfer between the main memory and the peripheral devices.
摘要翻译：一种计算机系统，其中主机总线从连接到输入/输出（I / O）总线（例如，外围设备）的主存储器和设备之间的数据传输负担中减轻。相反，本发明操作来将数据传输的大部分负担置于总线仲裁单元内的内部总线上，使得主机总线比传统实现更早地释放。此外，为了减少寻求通过主机总线和内部总线访问主存储器的处理器的停止，主总线能够在暂时不需要内部总线的时间期间使用内部总线来访问主存储器通过主存储器和外围设备之间的数据传输。因此，由于主机总线可用于其他处理操作，而不是与外围设备的数据传输相关联，因此内部总线在主存储器之间的数据传输期间偶尔被释放，因此计算机系统具有显着更好的性能和外围设备。

4. 发明授权

US5903773A System to improve trapping of I/O instructions in a peripheral component interconnect bus computer system and method therefor 失效
标题翻译：用于改善外围组件互连总线计算机系统中的I / O指令的捕获的系统及其方法
公开(公告)号：US5903773A
公开(公告)日：1999-05-11
申请号：US704281
申请日：1996-08-28
申请人： Nicholas Julian Richardson , Barry Davis , Gary Hicok
发明人： Nicholas Julian Richardson , Barry Davis , Gary Hicok
IPC分类号： G06F11/07 , G06F11/30
CPC分类号： G06F11/0745 , G06F11/0793
摘要： A system for trapping I/O instructions. The system is comprised of at least one peripheral controller for receiving a plurality of I/O instructions and for initiating trapping of an un-executable I/O instruction by issuing a target abort signal when the peripheral controller senses a power off condition in a peripheral device. A system controller is coupled to the at least one peripheral controller for receiving the target abort signal from the at least one peripheral controller and for sequentially: issuing a system management interrupt (SMI) signal; counting a predetermined time period to allow recognition of the SMI signal; and issuing a cycle completion signal after counting the predetermined time period. A CPU is coupled to the system controller for issuing a plurality of I/O instructions and for receiving the SMI signal and the cycle completion signal from the system controller.
摘要翻译：用于捕获I / O指令的系统。该系统包括至少一个外围控制器，用于接收多个I / O指令，并且用于当外设控制器感测到外围设备的电源关闭状态时，通过发出目标中止信号来开始捕获不可执行的I / O指令设备。系统控制器耦合到所述至少一个外围控制器，用于从所述至少一个外围控制器接收目标中止信号，并且用于顺序地：发出系统管理中断（SMI）信号; 计数预定时间段以允许SMI信号的识别; 以及在计数所述预定时间段之后发出循环完成信号。 CPU耦合到系统控制器，用于发出多个I / O指令，并用于从系统控制器接收SMI信号和循环完成信号。

5. 发明公开

US20230415959A1 Scent Indicators on Containers 审中-公开
公开(公告)号：US20230415959A1
公开(公告)日：2023-12-28
申请号：US17809349
申请日：2022-06-28
申请人： Barry Davis , Ansley Dunning
发明人： Barry Davis , Ansley Dunning
IPC分类号： B65D23/14 , B65D25/20 , B65D75/58 , A45D34/00 , B65D75/54
CPC分类号： B65D23/14 , B65D25/205 , B65D75/5805 , A45D34/00 , B65D75/54 , A45D2034/002
摘要： A device has a container containing scented substance. The container has a shroud coupled to an outside surface of the container. Further, the device has a scented piece that is covered by the shroud such that a customer grasps the shroud and pulls the shroud from the scented piece so that the customer can smell a scent emanating from the scented piece.

6. 发明申请

US20070065788A1 Method for developing a curriculum 审中-公开
标题翻译：制定课程的方法
公开(公告)号：US20070065788A1
公开(公告)日：2007-03-22
申请号：US11231163
申请日：2005-09-20
申请人： Barry Davis , Mark Scullard , Susanne Kukkonen , Jeffrey Sugerman
发明人： Barry Davis , Mark Scullard , Susanne Kukkonen , Jeffrey Sugerman
IPC分类号： G09B19/00
CPC分类号： G09B5/00
摘要： A method for developing a training curriculum from a pre-existing library of materials is provided. The method comprises: controlling selection of at least one set-up module from the pre-existing library; controlling selection of at least one closing module from the pre-existing library; and controlling selection of at least one insight module from the pre-existing library, wherein each insight module is sequence independent of the others. The method further comprises combining the set-up, closing and insight modules into a predefined set of learning materials.
摘要翻译：提供了一种从先前存在的材料库开发培训课程的方法。该方法包括：控制从先前存在的库中选择至少一个建立模块; 控制从先前存在的库中选择至少一个关闭模块; 以及控制从先前存在的库中选择至少一个洞察模块，其中每个洞察模块是与其他库独立的序列。该方法还包括将设置，关闭和洞察模块组合成预定义的一组学习材料。

7. 发明授权

US5925099A Method and apparatus for transporting messages between processors in a multiple processor system 失效
公开(公告)号：US5925099A
公开(公告)日：1999-07-20
申请号：US490651
申请日：1995-06-15
申请人： William T. Futral , Elliot Garbus , Barry Davis
发明人： William T. Futral , Elliot Garbus , Barry Davis
IPC分类号： G06F13/10 , G06F13/12 , G06F13/40 , G06F13/00
CPC分类号： G06F13/126 , G06F13/4059
摘要： A message unit that provides a hardware queue interface between a host processor and a local processor handling I/O operations in an I/O platform. Circuitry manages the head and tail pointers of an inbound free queue, an inbound post queue, an outbound free queue and an outbound post queue. Circuitry is also provided for enabling a host processor or bus agent to access these queues in a single bus transaction by reading or writing inbound port registers or outbound port registers. The queue elements contain handles of message buffers. The invention automatically performs the specific task of locating the next element in a queue, altering that element, and modifying a queue descriptor (i.e., a head or a tail pointer) to indicate the next element for a next queue access. A plurality of registers are used for selectively interrupting either the host processor or the local processor when the queues are written to by either the host processor, a bus agent, or the local processor.

8. 发明申请

US20050145089A1 Handi-guitar (for the handicapped guitar player) 有权
标题翻译：手吉他（用于残疾吉他手）
公开(公告)号：US20050145089A1
公开(公告)日：2005-07-07
申请号：US10916575
申请日：2004-08-12
申请人： Barry Davis
发明人： Barry Davis
IPC分类号： G10D3/00 , G10D3/08 , G10H5/00 , H04Q1/18
CPC分类号： G10D3/08
摘要： A thin flat body of clear plastic with a key pad (20) on the inside back base (12), and a chord scale (22) on the outside front of the base (10). The chord scale is fitted with braille nodules (24) for guiding the proper placement of the fingers on the EZ chord. On the bottom or lower side of the base (10) (12) is a gripping angle (14) for the learning chord device. On the top or upper side, and bottom or lower side of the base (10) (12) are gripping angles (14) (16) for the universal chord device. One EZ chord is a device that when manipulated by a human hand, or an artificial hand, is pressed and positioned onto the guitar neck, fret and strings to form and sound guitar chords and/or notes. The EZ chord devices can be used by mentally, physically, or visually handicapped people as well as non-handicapped people, to play and/or learn to play the guitar.
摘要翻译：一个透明塑料薄扁平体，内侧背部底座（12）上带有一个键盘（20），和一个在底座（10）的外侧前方的弦标（22）。弦标配有盲文结节（24），用于将手指正确放置在EZ弦上。在基座（10）（12）的底部或底侧上是用于学习弦装置的夹紧角（14）。在基座（10）（12）的顶部或上侧以及底侧或下侧是用于通用和弦装置的夹紧角（14）（16）。一个EZ和弦是一种装置，当用人的手或人造手操纵时，被按压并放置在吉他颈部上，装置和琴弦以形成吉他和弦和/或音符。 EZ和弦设备可以被智力，身体或视觉残疾人以及非残疾人使用，以播放和/或学习弹吉他。

9. 发明授权

US06353794B1 Air travel information and computer data compilation, retrieval and display method and system 有权
标题翻译：航空旅行信息和计算机数据汇编，检索和显示方法及系统
公开(公告)号：US06353794B1
公开(公告)日：2002-03-05
申请号：US09421167
申请日：1999-10-19
申请人： Barry Davis , Scott Blachowicz , Larry Brasfield , Dennis Howard , David Helms , Craig Paynter , Randy Robertson , James Rouse
发明人： Barry Davis , Scott Blachowicz , Larry Brasfield , Dennis Howard , David Helms , Craig Paynter , Randy Robertson , James Rouse
IPC分类号： G01C2100
CPC分类号： G08G5/0043 , G01C21/00 , G01C23/00 , G08G5/0095
摘要： A system, method, and computer program for managing integrated real-time information about air flight trips and providing that information to multiple users by way of a flight operations system (FOS), including a data engine (DE) and render engine (RE). A computerized Upstream Distribution Center (UDC) containing a packet manager connects to the FOS and to a user interface including a computer display using text, image and color. The UDC is connectable to multiple user interfaces containing copies of the computer program through computer networks by which information is collected and propagated on a real time basis using object-relational mapping, object caching and proactive notification or “push” technology.
摘要翻译：一种用于管理关于航空飞行旅行的综合实时信息并通过飞行操作系统（FOS）向多个用户提供信息的系统，方法和计算机程序，包括数据引擎（DE）和渲染引擎（RE）。包含分组管理器的计算机上行分发中心（UDC）连接到FOS，并连接到包括使用文本，图像和颜色的计算机显示器的用户界面。 UDC可通过计算机网络连接到包含计算机程序副本的多个用户界面，通过该网络，使用对象关系映射，对象缓存和主动通知或“推送”技术实时地收集和传播信息。

10. 发明授权

US5859987A Method and apparatus for providing multiple configuration reset modes for an intelligent bridge 失效
标题翻译：为智能桥提供多种配置复位模式的方法和装置
公开(公告)号：US5859987A
公开(公告)日：1999-01-12
申请号：US536156
申请日：1995-09-29
申请人： Byron Gillespie , Barry Davis
发明人： Byron Gillespie , Barry Davis
IPC分类号： G06F13/40
CPC分类号： G06F13/4027
摘要： An integrated circuit for providing multiple configuration modes in a multi-funtion intelligent bridge that includes an integrated processor. A first circuit, coupled to a first external bus, for selectively generating retry cycles onto the first external bus in response to a retry signal is provided. A second circuit, coupled to a local processor, for selectively resetting a local processor that is integrated in the intelligent bridge in response to a reset signal is provided. The first and second circuit, in conjunction with the retry signal and the reset signal, selectively provides one of a multiple number of configuration reset modes for the multi-function intelligent bridge.
摘要翻译：一种用于在包括集成处理器的多功能智能桥中提供多种配置模式的集成电路。提供耦合到第一外部总线的第一电路，用于响应于重试信号选择性地产生到第一外部总线上的重试周期。提供了耦合到本地处理器的第二电路，用于响应于复位信号选择性地复位集成在智能桥中的本地处理器。第一和第二电路结合重试信号和复位信号，选择性地为多功能智能桥提供多种配置复位模式之一。

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