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11. 发明申请

US20130159809A1 Error Detection And Correction Of A Data Transmission 有权
标题翻译：数据传输的错误检测和纠正
公开(公告)号：US20130159809A1
公开(公告)日：2013-06-20
申请号：US13524804
申请日：2012-06-15
申请人： Alfredo Aldereguia , Clifton E. Kerr , Grace A. Richter
发明人： Alfredo Aldereguia , Clifton E. Kerr , Grace A. Richter
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04L1/0045 , H03M13/09 , H03M13/098 , H03M13/2906 , H03M13/2927 , H04L1/0061
摘要： Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word.
摘要翻译：数据传输的错误检测和校正包括：接收数据块，其中该块包括预定数量的字，其中每个字包括奇偶校验位，其中该数据块也是纠错码（ECC）; 根据单词的奇偶校验位来确定每个单词是否包括奇偶校验错误; 提交不包括奇偶校验错误的每个单词，如果块中仅有一个单词包含奇偶校验错误：通过使用块的ECC并提交校正字来校正包括奇偶校验错误的一个单词。

12. 发明申请

US20120204021A1 Updating Programmable Logic Devices 有权
标题翻译：更新可编程逻辑器件
公开(公告)号：US20120204021A1
公开(公告)日：2012-08-09
申请号：US13443329
申请日：2012-04-10
申请人： Alfredo Aldereguia , Grace A. Richter , William B. Schwartz
发明人： Alfredo Aldereguia , Grace A. Richter , William B. Schwartz
IPC分类号： G06F15/177
CPC分类号： G06F15/177 , G06F1/24 , G06F8/65 , G06F9/00 , G06F9/4401 , G06F9/4406 , G06F21/572
摘要： Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter.
摘要翻译：在对称多处理（“SMP”）计算机中更新可编程逻辑器件（“PLD”），SMP计算机的每个计算节点包括耦合用于通过总线适配器进行数据通信的PLD，总线适配器适于通过一组一个或多个输入/输出（'I / O'）存储器地址，包括使用PLD的配置指令的更新配置主计算节点; 在引导时，PLD在SMP引导中为每个计算节点上的每个总线适配器分配独特的一组一个或多个I / O地址; 并且在SMP引导期间由主计算节点向所有计算节点提供更新，通过每个总线适配器以唯一的单独的一个或多个I / O地址集合将更新作为数据传输写入每个PLD 为每个总线适配器。

13. 发明授权

US08225081B2 Updating programmable logic devices 有权
标题翻译：更新可编程逻辑器件
公开(公告)号：US08225081B2
公开(公告)日：2012-07-17
申请号：US12486132
申请日：2009-06-17
申请人： Alfredo Aldereguia , Grace A. Richter , William B. Schwartz
发明人： Alfredo Aldereguia , Grace A. Richter , William B. Schwartz
IPC分类号： G06F15/177
CPC分类号： G06F15/177 , G06F1/24 , G06F8/65 , G06F9/00 , G06F9/4401 , G06F9/4406 , G06F21/572
摘要： Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter.
摘要翻译：在对称多处理（“SMP”）计算机中更新可编程逻辑器件（“PLD”），SMP计算机的每个计算节点包括耦合用于通过总线适配器进行数据通信的PLD，总线适配器适于通过一组一个或多个输入/输出（'I / O'）存储器地址，包括使用PLD的配置指令的更新配置主计算节点; 在引导时，PLD在SMP引导中为每个计算节点上的每个总线适配器分配独特的一组一个或多个I / O地址; 并且在SMP引导期间由主计算节点向所有计算节点提供更新，通过每个总线适配器以唯一的单独的一个或多个I / O地址集合将更新作为数据传输写入每个PLD 为每个总线适配器。

14. 发明授权

US07523365B2 Dynamic determination of signal quality in a digital system 有权
标题翻译：数字系统中信号质量的动态确定
公开(公告)号：US07523365B2
公开(公告)日：2009-04-21
申请号：US11305932
申请日：2005-12-19
申请人： Alfredo Aldereguia , Marcus Alan Baker , Justin Potok Bandholz , Jeffrey Buchanan Williams
发明人： Alfredo Aldereguia , Marcus Alan Baker , Justin Potok Bandholz , Jeffrey Buchanan Williams
IPC分类号： G01R31/28 , G06F11/00 , G11B27/00 , H04B3/46
CPC分类号： G11B20/10009
摘要： A receiving processor is configured with a normal (operational) path and a test path. The test path is configured in parallel with the normal path. The test path simulates and receives as input the same data as the normal path, but the test path has a separate voltage reference (Vref—test) which is applied to a test input buffer. The same data input to normal buffer is also input to the test buffer. The output of the test buffer is input to a test latch. A clocking signal supplied to the test latch is a variable clocking signal enabling the clock signal to be skewed selectively. The output of the test latch is compared with the output of the normal latch, and differences between the two output signals defines an error for a particular voltage/clock-skew combination.
摘要翻译：接收处理器配置有正常（可操作）路径和测试路径。测试路径与正常路径并行配置。测试路径模拟并接收与正常路径相同的数据作为输入，但是测试路径具有单独的参考电压（Vref - 测试），该参考电压被施加到测试输入缓冲器。与正常缓冲区相同的数据输入也输入到测试缓冲区。测试缓冲器的输出被输入到测试锁存器。提供给测试锁存器的时钟信号是使时钟信号有选择地偏斜的可变时钟信号。将测试锁存器的输出与正常锁存器的输出进行比较，两个输出信号之间的差异定义了特定电压/时钟偏移组合的误差。

15. 发明申请

US20050196124A1 Automated topology detection in a data processing system 审中-公开
标题翻译：数据处理系统中的自动拓扑检测
公开(公告)号：US20050196124A1
公开(公告)日：2005-09-08
申请号：US10777508
申请日：2004-02-12
申请人： Alfredo Aldereguia , Ralph Begun , Grace Richter
发明人： Alfredo Aldereguia , Ralph Begun , Grace Richter
IPC分类号： G02B6/00
CPC分类号： G06F13/4265
摘要： A data processing system suitable for use in a scalable system, including a first set of processors, a first system memory, and scalability logic to connect the data processing system to a second data processing system to form a scaled system. A set of scalability ports are connected to the scalability logic to receive scalability cables connecting the first system to the second system or to another processor board within the same chassis. The system includes system management to cause each of the system's scalability ports to issue an identifiable signal. System management also detects the reception of an identifiable signal, sent by another system, received by any of the scalability ports and reports the reception of the signal to a system management of the second system to determine which ports of the two systems are connected by the cable.
摘要翻译：一种适用于可扩展系统的数据处理系统，包括第一组处理器，第一系统存储器和可扩展性逻辑，以将数据处理系统连接到第二数据处理系统以形成缩放系统。一组可扩展性端口连接到可扩展性逻辑，以接收将第一系统连接到第二系统或同一机架内的另一处理器板的可伸缩电缆。该系统包括系统管理，以使每个系统的可扩展端口发出可识别的信号。系统管理还检测由另一系统发送的可识别信号的接收，由任何可扩展端口接收，并将信号的接收报告给第二系统的系统管理，以确定两个系统的哪些端口由电缆。

16. 发明授权

US5761533A Computer system with varied data transfer speeds between system components and memory 失效
标题翻译：计算机系统在系统组件和内存之间具有不同的数据传输速度
公开(公告)号：US5761533A
公开(公告)日：1998-06-02
申请号：US293411
申请日：1994-08-19
申请人： Alfredo Aldereguia , Nader Amini , Daryl Carvis Cromer , Richard Louis Horne , Ashu Kohli , Kimberly Kibbe Sendlein , Cang Ngoc Tran
发明人： Alfredo Aldereguia , Nader Amini , Daryl Carvis Cromer , Richard Louis Horne , Ashu Kohli , Kimberly Kibbe Sendlein , Cang Ngoc Tran
IPC分类号： G06F13/42 , G06F13/16 , H01J1/00
CPC分类号： G06F13/1689
摘要： A computer system is provided, comprising system memory and a memory controller which resides on a system bus for controlling access to the system memory, a bus interface unit and a direct memory access controller also residing on the system bus, and a central processing unit electrically connected with the memory controller which is able to read and write data to the system memory via the memory controller. The memory controller and the bus interface unit each operate, when either is in control of the system bus, at a clock frequency which is a multiple of the clock frequency at which the direct memory access controller operates on the system bus. The memory controller and the bus interface unit each operate, when the direct memory access controller is in control of the system bus, at the same clock frequency as that of the direct memory access controller. The clock frequencies of the memory controller, the bus interface unit and the direct memory access controller are each synchronized in time. The computer system thereby permits system bus devices, operating at different clock frequencies, to coexist on the system bus without hindering the performance of the faster speed devices.
摘要翻译：提供了一种计算机系统，包括系统存储器和驻留在用于控制对系统存储器的访问的系统总线上的存储器控制器，总线接口单元和也驻留在系统总线上的直接存储器访问控制器，以及电子与能够通过存储器控制器将数据读取和写入系统存储器的存储器控制器连接。当存储器控制器和总线接口单元在控制系统总线时都以在直接存储器访问控制器在系统总线上操作的时钟频率的倍数的时钟频率下操作。当直接存储器存取控制器处于系统总线的控制状态时，存储器控制器和总线接口单元在与直接存储器存取控制器相同的时钟频率下操作。存储器控制器，总线接口单元和直接存储器访问控制器的时钟频率各自在时间上同步。因此，计算机系统允许以不同时钟频率工作的系统总线设备在系统总线上共存而不会妨碍更快速的设备的性能。

17. 发明授权

US5255374A Bus interface logic for computer system having dual bus architecture 失效
标题翻译：具有双总线架构的计算机系统的总线接口逻辑
公开(公告)号：US5255374A
公开(公告)日：1993-10-19
申请号：US816203
申请日：1992-01-02
申请人： Alfredo Aldereguia , Nader Amini , Richard L. Horne , Terence J. Lohman , Cang N. Tran
发明人： Alfredo Aldereguia , Nader Amini , Richard L. Horne , Terence J. Lohman , Cang N. Tran
IPC分类号： G06F13/36 , G06F13/16 , G06F13/14
CPC分类号： G06F13/1684
摘要： A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit. The predetermined set of operating conditions occur when (i) the memory controller on behalf of the central processing unit writes data to the input/output device, or (ii) the memory controller on behalf of the central processing unit initiates a read or write cycle destined for the input/output device acting as a slave on the input/output bus, and the data bus width of the memory controller is greater than a corresponding data bus width of the input/output device.

18. 发明授权

US08560807B2 Accessing a logic device through a serial interface 失效
标题翻译：通过串行接口访问逻辑设备
公开(公告)号：US08560807B2
公开(公告)日：2013-10-15
申请号：US13325432
申请日：2011-12-14
申请人： Alfredo Aldereguia , James J. Parsonese , Grace A. Richter , Christopher L. Wood
发明人： Alfredo Aldereguia , James J. Parsonese , Grace A. Richter , Christopher L. Wood
IPC分类号： G06F12/00
CPC分类号： G06F12/02 , G06F2212/206 , H03K19/173
摘要： Methods, apparatuses, and computer program products for accessing a logic device through a serial interface are provided. Embodiments include receiving, by the serial interface of the logic device, a first data access request indicating a non-linear address mode, wherein the first data access request includes: a non-linear address corresponding to a non-linear index specifying a plurality of non-linear addresses, the non-linear index associating each non-linear address with one of the plurality of registers; a data count indicating an amount of data to be accessed in the first data access request; and a page offset value indicating within a register, a starting page to perform the first data access request. Embodiments also include identifying in the non-linear address mode a location within the logic device based on the non-linear address and the starting page; and performing at the identified location, by the logic device, a serial transaction in accordance with the first data access request.
摘要翻译：提供了通过串行接口访问逻辑设备的方法，设备和计算机程序产品。实施例包括通过逻辑设备的串行接口接收指示非线性地址模式的第一数据访问请求，其中第一数据访问请求包括：与非线性索引对应的非线性地址，其指定多个非线性地址，所述非线性索引将每个非线性地址与所述多个寄存器之一相关联; 指示在第一数据访问请求中要访问的数据量的数据计数; 以及指示在寄存器内的页面偏移值，用于执行第一数据访问请求的起始页。实施例还包括基于非线性地址和起始页在非线性地址模式中识别逻辑设备内的位置; 以及通过逻辑设备在所识别的位置处执行根据第一数据访问请求的串行事务。

19. 发明申请

US20130159592A1 Accessing A Logic Device Through A Serial Interface 失效
标题翻译：通过串行接口访问逻辑器件
公开(公告)号：US20130159592A1
公开(公告)日：2013-06-20
申请号：US13325432
申请日：2011-12-14
申请人： Alfredo Aldereguia , James J. Parsonese , Grace A. Richter , Christopher L. Wood
发明人： Alfredo Aldereguia , James J. Parsonese , Grace A. Richter , Christopher L. Wood
IPC分类号： G06F13/36
CPC分类号： G06F12/02 , G06F2212/206 , H03K19/173
摘要： Methods, apparatuses, and computer program products for accessing a logic device through a serial interface are provided. Embodiments include receiving, by the serial interface of the logic device, a first data access request indicating a non-linear address mode, wherein the first data access request includes: a non-linear address corresponding to a non-linear index specifying a plurality of non-linear addresses, the non-linear index associating each non-linear address with one of the plurality of registers; a data count indicating an amount of data to be accessed in the first data access request; and a page offset value indicating within a register, a starting page to perform the first data access request. Embodiments also include identifying in the non-linear address mode a location within the logic device based on the non-linear address and the starting page; and performing at the identified location, by the logic device, a serial transaction in accordance with the first data access request.
摘要翻译：提供了通过串行接口访问逻辑设备的方法，设备和计算机程序产品。实施例包括通过逻辑设备的串行接口接收指示非线性地址模式的第一数据访问请求，其中第一数据访问请求包括：对应于非线性索引的非线性地址，其指定多个非线性地址，所述非线性索引将每个非线性地址与所述多个寄存器之一相关联; 指示在第一数据访问请求中要访问的数据量的数据计数; 以及指示在寄存器内的页面偏移值，用于执行第一数据访问请求的起始页。实施例还包括基于非线性地址和起始页在非线性地址模式中识别逻辑设备内的位置; 以及通过逻辑设备在所识别的位置处执行根据第一数据访问请求的串行事务。

20. 发明授权

US07627800B2 Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol 有权
标题翻译：与能够根据地址前缀串行总线协议进行操作的设备进行错误检查通信
公开(公告)号：US07627800B2
公开(公告)日：2009-12-01
申请号：US11419533
申请日：2006-05-22
申请人： Alfredo Aldereguia , Grace A. Richter , Jeffrey B. Williams
发明人： Alfredo Aldereguia , Grace A. Richter , Jeffrey B. Williams
IPC分类号： H03M13/47
CPC分类号： G06F11/1008
摘要： Methods, apparatus, and computer program products are disclosed for communicating with error checking to a device capable of operating according to an address prefix serial bus protocol that includes identifying whether the device supports error checking, and if the device supports error checking: setting the device in an error checking mode and sending a message with error checking data to the device. Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol may include performing an error checking operation on the message to obtain error checking data. Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol may include retrieving the device's error checking capability from a device table.
摘要翻译：公开了用于与能够根据地址前缀串行总线协议进行操作的设备进行错误检查的方法，装置和计算机程序产品，该地址前缀串行总线协议包括识别设备是否支持错误检查，以及设备是否支持错误检查：设置设备在错误检查模式下，向设备发送带有错误检查数据的消息。与能够根据地址前缀串行总线协议进行操作的设备进行错误检查通信可以包括对消息进行错误检查操作以获得错误检查数据。与能够根据地址前缀串行总线协议进行操作的设备进行错误检查通信可能包括从设备表检索设备的错误检查功能。

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