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11. 发明申请

US20100026348A1 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 有权
标题翻译：高信号电平输入/输出电路
公开(公告)号：US20100026348A1
公开(公告)日：2010-02-04
申请号：US12181655
申请日：2008-07-29
申请人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03K3/00 , H03L5/00
CPC分类号： H03K19/00315 , H03K19/017581 , H03K19/018507
摘要： A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.
摘要翻译：用于接口电路的信号驱动器具有第一级电平移位器，以接收输入信号并以第一信号电平输出信号。信号驱动器还具有耦合到第一级电平移位器的第二级电平移位器，以在第二信号电平输出信号。第一级和第二级电平移位器的电子部件具有小于第二信号电平的可靠性限制。第一级电平移位器和第二级电平转换器的第一和第二级配置防止当处理用于在第二信号电平输出的信号时将电子部件暴露于高于可靠性限制的端对端信号电平。

12. 发明申请

US20090033400A1 VOLTAGE TOLERANT FLOATING N-WELL CIRCUIT 有权
标题翻译：电压稳压浮动N电路
公开(公告)号：US20090033400A1
公开(公告)日：2009-02-05
申请号：US11832128
申请日：2007-08-01
申请人： Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03L5/00
CPC分类号： H03K19/018592 , H03K19/00384
摘要： Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.
摘要翻译：提出了用于耐压漂浮N阱电路的方法和装置。提供了一种用于减轻由输入电压引起的漏电流的装置，其包括具有耦合到正电压源的源极和耦合到浮动节点的漏极的第一晶体管。该装置还可以包括耦合到负电压源和第一晶体管的可控下拉通路，其中可控下拉通道被配置为在第一状态期间导通第一晶体管并上拉浮动节点。该装置还可以包括具有耦合到第一晶体管的栅极的源极和耦合到浮动节点的漏极的第二晶体管，其中第二晶体管被配置为在第二状态期间将浮动节点置于浮动电位。

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