会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 173. 发明授权
    • Switching of MRAM devices having soft magnetic reference layers
    • 具有软磁参考层的MRAM器件的切换
    • US07193889B2
    • 2007-03-20
    • US10776061
    • 2004-02-11
    • Manish Sharma
    • Manish Sharma
    • G11C11/00
    • G11C11/15
    • A magnetic random access memory (MRAM) that includes an array of magnetic memory cells and a plurality of word and bit lines connecting columns and rows of the memory cells so that the memory cells are positioned at cross-points of the word and bit lines. Each memory cell has a magnetic reference layer and a magnetic data layer. Each magnetic reference layer and each magnetic data layer has a magnetization that is switchable between two states under the influence of a magnetic field and each reference layer has at a first temperature a coercivity that is lower than that of each data layer at the first temperature. The MRAM also includes a plurality of heating elements each proximate to a respective data layer. Each heating element provides in use for localized heating of the respective data layer to reduce the coercivity of the data layer so as to facilitate switching of the data layer.
    • 磁性随机存取存储器(MRAM),其包括磁存储器单元阵列和连接存储器单元的列和行的多个字和位线,使得存储器单元位于字和位线的交叉点处。 每个存储单元具有磁性参考层和磁性数据层。 每个磁参考层和每个磁数据层具有在磁场影响下在两个状态之间切换的磁化,并且每个参考层在第一温度下具有低于第一温度下每个数据层的矫顽力的矫顽力。 MRAM还包括各自靠近相应数据层的多个加热元件。 每个加热元件用于各个数据层的局部加热,以降低数据层的矫顽力,从而便于切换数据层。
    • 176. 发明申请
    • Sensor array using sail
    • 传感器阵列使用帆
    • US20060270057A1
    • 2006-11-30
    • US11138619
    • 2005-05-26
    • Manish Sharma
    • Manish Sharma
    • G01N1/00
    • G01N27/4145Y10T436/25
    • Provided is a sensor array and a method of forming the same. The sensor array includes an array of apertures etched into a 3D patterned resist layer to expose areas of one or more agents and/or reagents deposited on a substrate. The sensor is formed using a Self-Aligned Imprint Lithography (“SAIL”) method, a process that allows for a one-time deposition of all required materials followed by a series of etching/cleaning steps. The location of reagents on the sensor template, as well as the concentration gradient of each reagent, may be controlled through the sensor manufacturing process. Bores of a single reagent, or bores containing two or more reagents, may be formed using the SAIL process.
    • 提供一种传感器阵列及其形成方法。 传感器阵列包括刻蚀成3D图案化抗蚀剂层的孔的阵列,以暴露沉积在基底上的一种或多种试剂和/或试剂的区域。 传感器使用自对准印迹光刻(“SAIL”)方法形成,该方法允许一次性沉积所有所需材料,然后进行一系列蚀刻/清洁步骤。 传感器模板上的试剂位置以及各试剂的浓度梯度可通过传感器制造过程进行控制。 可以使用SAIL方法形成单个试剂的孔或包含两种或更多种试剂的孔。
    • 179. 发明授权
    • Method and apparatus for deriving a bounded set of path delay test patterns covering all transition faults
    • 用于导出覆盖所有过渡故障的有界路径延迟测试模式集的方法和装置
    • US07039845B2
    • 2006-05-02
    • US10109018
    • 2002-03-28
    • Jeff RearickManish Sharma
    • Jeff RearickManish Sharma
    • G06F11/00
    • G01R31/318328G01R31/31813G01R31/31917
    • A method and apparatus for generating test patterns used to test an integrated circuit (IC). The apparatus comprises first logic for determining a subset of transition fault sites on an IC to be tested, second logic that identifies a longest sensitizable path through each transition fault site of the subset of transition fault sites, and third logic that generates a bounded set of test patterns that test the identified longest sensitizable paths through each transition fault site of the subset of transition fault sites. The present invention combines various aspects of transition fault modeling and path delay fault modeling to enable global delay testing of an IC within reasonable amount of time.
    • 一种用于产生用于测试集成电路(IC)的测试图案的方法和装置。 该设备包括用于确定要测试的IC上的过渡故障点的子集的第一逻辑,识别通过过渡故障位置子集的每个过渡故障位点的最长可敏化路径的第二逻辑,以及生成有限组的 测试模式,通过过渡故障点子集的每个过渡故障点测试识别的最长敏感路径。 本发明结合了转换故障建模和路径延迟故障建模的各个方面,以在合理的时间量内实现IC的全局延迟测试。
    • 180. 发明申请
    • Determining and analyzing integrated circuit yield and quality
    • 确定和分析集成电路产量和质量
    • US20060066339A1
    • 2006-03-30
    • US11221395
    • 2005-09-06
    • Janusz RajskiGang ChenMartin KeimNagesh TamarapalliManish SharmaHuaxing Tang
    • Janusz RajskiGang ChenMartin KeimNagesh TamarapalliManish SharmaHuaxing Tang
    • G01R31/26
    • G06F11/2273G01R31/01G01R31/2846G01R31/2853G01R31/2894G01R31/31704G01R31/31835
    • Methods, apparatus, and systems for computing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein, information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.
    • 本文公开了用于计算,分析和改进集成电路产量和质量的方法,装置和系统。 例如,在本文公开的一个示例性方法中,从设计用于电子设备中的功能使用的集成电路的处理测试响应中接收信息。 在该实施例中,该信息表示在集成电路测试期间观察到的集成电路故障以及导致集成电路故障的可能的产量限制因素。 通过统计分析接收的信息来确定集成电路中的一个或多个可能的屈服限制因素实际上引起集成电路故障的概率。 报告了一个或多个可能的屈服限制因素实际上导致集成电路故障的概率。 还公开了包括用于使计算机执行任何所述方法的计算机可执行指令的有形计算机可读介质。