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161. 发明授权

US5805003A Clock frequency synthesis using delay-locked loop 失效
标题翻译：使用延迟锁定环路的时钟频率合成
公开(公告)号：US5805003A
公开(公告)日：1998-09-08
申请号：US921420
申请日：1997-08-29
申请人： Chuan-Ding Arthur Hsu
发明人： Chuan-Ding Arthur Hsu
IPC分类号： H03K5/13 , H03K5/156 , H03L7/081 , H03L7/16 , H03K5/159
CPC分类号： H03K5/133 , H03K5/1565 , H03L7/0812 , H03L7/16
摘要： A circuit for synthesizing, from a first signal having a first frequency, a second signal having a second frequency. This synthesis includes using a delay locked loop in combination with a minimal amount of logic circuitry to generate a synthesized output signal which is completely deterministic and does not require any analog control.
摘要翻译：一种用于从具有第一频率的第一信号中合成具有第二频率的第二信号的电路。该合成包括使用延迟锁定环与最小量的逻辑电路组合以产生完全确定性并且不需要任何模拟控制的合成输出信号。

162. 发明授权

US5757239A Direct digital synthesizer driven phase lock loop frequency synthesizer with clean up phase lock loop 失效
标题翻译：直接数字合成器驱动锁相环频率合成器，具有清理锁相环
公开(公告)号：US5757239A
公开(公告)日：1998-05-26
申请号：US780472
申请日：1997-01-08
申请人： Robert P. Gilmore
发明人： Robert P. Gilmore
IPC分类号： H03L7/16 , H03L7/18 , H03L7/22 , H03L7/23 , H03K3/80
CPC分类号： H03L7/22 , H03L7/1806 , H03L7/23
摘要： A frequency synthesizer which uses a direct digital synthesizer (DDS) to generate a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. The DDS output signal is bandpass filtered utilizing a clean-up phase lock loop (PLL) to produce a spectrally pure reference signal and promote overall fast settling time. A second or primary phase lock loop, having a much faster settling time than the first PLL, adjusts the frequency of the reference signal generated by the clean-up PLL. In one embodiment, the DDS frequency synthesizer has a digital to analog (DAC) converter coupled to the clean-up PLL. Another embodiment uses a modified DDS (without a DAC or lookup table) and feeds the most significant bit (MSB) or overflow bit from the DAC accumulator into the "clean-up" PLL. In both embodiments, the resulting synthesizer has high spectral purity, fine frequency resolution and a fast settling time. Yet another embodiment uses a switching apparatus to bypass the "clean-up" PLL while it is settling on a new frequency. Once the "clean-up" PLL settles on the new frequency the switches are set to couple the "clean-up" PLL back into the synthesizer apparatus.
摘要翻译：一种频率合成器，其使用直接数字合成器（DDS）来产生从多个参考频率中选择的频率的高度精确的周期信号。使用清理锁相环（PLL）对DDS输出信号进行带通滤波，以产生光谱纯参考信号，并促进整体快速建立时间。具有比第一PLL更快的建立时间的第二或主要锁相环调整由清理PLL产生的参考信号的频率。在一个实施例中，DDS频率合成器具有耦合到清理PLL的数模转换器（DAC）转换器。另一个实施例使用修改的DDS（没有DAC或查找表），并将来自DAC累加器的最高有效位（MSB）或溢出位馈送到“清理”PLL。在两个实施例中，所得的合成器具有高光谱纯度，精细的频率分辨率和快速的建立时间。另一个实施例使用开关装置来绕过“清理”PLL，同时在新频率上稳定。一旦“清理”PLL固定在新频率上，则开关被设置为将“清理”PLL耦合回合成器装置。

163. 发明授权

US5650754A Phase-loched loop circuits and voltage controlled oscillator circuits 失效
标题翻译：相位环路电路和压控振荡器电路
公开(公告)号：US5650754A
公开(公告)日：1997-07-22
申请号：US389710
申请日：1995-02-15
申请人： Shankar R. Joshi , Ulrich L. Rohde , Klaus Eichel
发明人： Shankar R. Joshi , Ulrich L. Rohde , Klaus Eichel
IPC分类号： H03B1/00 , H03B1/04 , H03B5/12 , H03J3/18 , H03L7/08 , H03L7/099 , H03L7/183 , H03L7/16
CPC分类号： H03L7/183 , H03B5/1243 , H03J3/185 , H03L7/08 , H03L7/099 , H03B2201/0208 , H03B2202/08 , H03L2207/06 , H03L2207/10
摘要： Voltage controlled oscillator (VCO) circuits include a VCO and voltage regulator provided on an integrated VCO module, balanced control input for the VCO, buffering of the VCO and frequency multiplication of the VCO output signal. Such improved VCO circuits are especially useful in phase-locked loop (PLL) circuits. Improved PLL circuits are also provided, including a PLL circuit with separate analog and digital grounds.
摘要翻译：压控振荡器（VCO）电路包括集成VCO模块上的VCO和稳压器，VCO的平衡控制输入，VCO的缓冲和VCO输出信号的倍频。这种改进的VCO电路在锁相环（PLL）电路中特别有用。还提供了改进的PLL电路，包括具有独立模拟和数字接地的PLL电路。

164. 发明授权

US5631587A Frequency synthesizer with adaptive loop bandwidth 失效
标题翻译：具有自适应环路带宽的频率合成器
公开(公告)号：US5631587A
公开(公告)日：1997-05-20
申请号：US321430
申请日：1994-10-11
申请人： Ramon S. Co , Howard C. Yang
发明人： Ramon S. Co , Howard C. Yang
IPC分类号： H03L7/089 , H03L7/093 , H03L7/107 , H03L7/183 , H03L7/16 , H03L7/00
CPC分类号： H03L7/0898 , H03L7/093 , H03L7/107 , H03L7/183 , H03L2207/04
摘要： A method for a frequency synthesizer with adaptive loop bandwidth is disclosed, which is adjusted by the improved frequency synthesizer includes a phase-locked loop and a phase-locked loop adjustment circuit. The phase-locked loop has loop characteristics including a loop bandwidth, a natural frequency, a damping factor, and the like. The phase-locked loop adjustment circuit is adjusted in response to a change in output frequency.
摘要翻译：公开了一种具有自适应环路带宽的频率合成器的方法，该方法由改进的频率合成器调节，包括锁相环和锁相环调节电路。锁相环具有包括环路带宽，固有频率，阻尼因子等的环路特性。响应于输出频率的变化来调节锁相环调节电路。

165. 发明授权

US5627498A Multiple frequency oscillator 失效
标题翻译：多频振荡器
公开(公告)号：US5627498A
公开(公告)日：1997-05-06
申请号：US598953
申请日：1996-02-09
申请人： Charles S. Meyer
发明人： Charles S. Meyer
IPC分类号： H03B5/36 , H03B25/00 , H03K3/03 , H03L7/16
CPC分类号： H03B25/00 , H03B5/368 , H03K3/03 , H03B2200/004 , H03B2200/0062
摘要： An oscillator comprises a first inverter provided with a resonant feedback circuit, a second inverter having its signal input terminal at the same DC level as the signal input terminal of the first inverter, and a current source having a current supply terminal connected to the power supply terminals of the first and second inverters.
摘要翻译：振荡器包括设置有谐振反馈电路的第一反相器，具有与第一反相器的信号输入端子相同的直流电平的信号输入端子的第二反相器，以及具有连接到电源的电流源端子的电流源第一和第二逆变器的端子。

166. 发明授权

US5572168A Frequency synthesizer having dual phase locked loops 失效
标题翻译：频率合成器具有双锁相环
公开(公告)号：US5572168A
公开(公告)日：1996-11-05
申请号：US513195
申请日：1995-08-09
申请人： Sanjay Kasturia
发明人： Sanjay Kasturia
IPC分类号： H03L7/197 , H03B21/00 , H03K3/0231 , H03K3/03 , H03K23/66 , H03L7/099 , H03L7/193 , H03L7/22 , H03L7/23 , H03L7/07 , H03L7/16
CPC分类号： H03K3/0231 , H03K23/66 , H03K23/667 , H03K3/03 , H03K3/0322 , H03L7/0995 , H03L7/23 , H03L7/193
摘要： A frequency synthesizer circuit for the front end of an RF system. The frequency synthesizer uses two pulse-swallow phase-locked loops in a synthesizer architecture that produces an output frequency that is a function of the two reference frequencies used as inputs into the two phase-locked loops. As a result, the frequency synthesizer can be incremented in steps equal to the differential of the reference frequencies of the two phase-locked loops, while the frequency outputs of each of the phase-locked loops can be incremented in much larger steps. This enables the two phase-locked loops to employ relatively large bandwidths, thereby achieving a faster signal lock as well as a better suppression of the voltage controlled oscillator (VCO) phase noise in each loop. The use of a dual loop synthesizer architecture allows for feedback correction of the VCO phase noise outside the loop bandwidth.
摘要翻译：用于RF系统前端的频率合成器电路。频率合成器在合成器架构中使用两个脉冲 - 吞咽锁相环，其产生作为用作两个锁相环路的输入的两个参考频率的函数的输出频率。结果，频率合成器可以以等于两个锁相环的参考频率的差的步长递增，而每个锁相环的频率输出可以以更大的步长递增。这使得两个锁相环能够采用相对较大的带宽，从而实现更快的信号锁定以及更好地抑制每个环路中的压控振荡器（VCO）相位噪声。使用双回路合成器架构允许在环路带宽之外的VCO相位噪声的反馈校正。

167. 发明授权

US5548249A Clock generator and method for generating a clock 失效
标题翻译：时钟发生器和用于产生时钟的方法
公开(公告)号：US5548249A
公开(公告)日：1996-08-20
申请号：US443577
申请日：1995-05-17
申请人： Masaya Sumita , Toshinori Maeda , Toru Kakiage
发明人： Masaya Sumita , Toshinori Maeda , Toru Kakiage
IPC分类号： H03L7/14 , H03L7/183 , H03L7/08 , H03L7/16
CPC分类号： H03L7/14 , H03L7/183
摘要： The clock generator of this invention includes: an input shutoff control circuit for receiving a base clock and a reference clock and outputting a first signal and a second signal in response to a reset signal, a phase comparator for outputting a phase difference signal indicating a phase difference between the first signal and the second signal; a voltage control oscillator for outputting a frequency variable clock in correspondence with the phase difference signal; and a voltage fixing control circuit for controlling a voltage of the phase difference signal in response to the reset signal, wherein, when the reset signal is in a first level, the input shutoff control circuit: outputs the base clock to the phase comparator as the first signal and outputs the reference clock to the phase comparator as the second signal, and the voltage fixing control circuit holds the voltage of the phase difference signal, and when the reset signal is in a second level different from the first level, the input shutoff control circuit outputs two signals to the phase comparator as the first signal and the second signal, the phase difference between the two signals being substantially zero, and the voltage fixing control circuit fixing the voltage of the phase difference signal to a predetermined voltage at which the voltage control oscillator does not oscillate.
摘要翻译：本发明的时钟发生器包括：输入切断控制电路，用于接收基准时钟和参考时钟，并响应复位信号输出第一信号和第二信号;相位比较器，用于输出指示相位的相位差信号第一信号和第二信号之间的差; 电压控制振荡器，用于输出与所述相位差信号相对应的频率可变时钟; 以及电压固定控制电路，用于响应于所述复位信号来控制所述相位差信号的电压，其中，当所述复位信号处于第一电平时，所述输入关断控制电路将所述基准时钟输出到所述相位比较器第一信号并将参考时钟作为第二信号输出到相位比较器，并且电压固定控制电路保持相位差信号的电压，并且当复位信号处于与第一电平不同的第二电平时，输入关断控制电路将作为第一信号和第二信号的两个信号输出到相位比较器，两个信号之间的相位差基本为零，并且电压固定控制电路将相位差信号的电压固定为预定电压，电压控制振荡器不振荡。

168. 发明授权

US5508659A Single loop frequency synthesizer with direct digital synthesis 失效
标题翻译：具有直接数字合成的单回路频率合成器
公开(公告)号：US5508659A
公开(公告)日：1996-04-16
申请号：US364988
申请日：1994-12-28
申请人： Elie Brunet , Jean-Noel Brasselet , Eric Souchard
发明人： Elie Brunet , Jean-Noel Brasselet , Eric Souchard
IPC分类号： H03L7/185 , H03L7/187 , H03L7/08 , H03L7/16 , H03L7/18
CPC分类号： H03L7/185 , H03L7/187
摘要： A frequency synthesizer with very short acquisition times. With a single loop there is associated a direct digital synthesizer whose signal is injected into the loop by means of a mixer. The adjustment of the loop is done on Np.Fr and the adjustment of the digital synthesis is done on (Ns+)Fr with Np, Ns, K and M as integers, Np being greater than Ns, 0.ltoreq.K
摘要翻译：频率合成器具有非常短的采集时间。通过单个循环，将一个直接数字合成器与信号通过混频器注入到环路中。循环的调整是在Np.Fr上完成的，数字合成的调整是以Np，Ns，K和M作为整数进行的（Ns +）Fr，Np大于Ns，0 <= K

169. 发明授权

US5410742A SAW electric part and frequency conversion circuit 失效
标题翻译： SAW电器部分和变频电路
公开(公告)号：US5410742A
公开(公告)日：1995-04-25
申请号：US195904
申请日：1994-02-14
申请人： Kotaro Yajima
发明人： Kotaro Yajima
IPC分类号： H03L7/16 , H03B5/04 , H03B5/32 , H03D7/00 , H03H9/25 , H04B1/26 , H04B1/16 , H01L41/08
CPC分类号： H03B5/326 , H03D7/00 , H03B2200/0018 , H03B2200/0022 , H03B5/04 , H03D2200/0017 , H03D2200/0096
摘要： According to this invention, an SAW electric part includes an SAW filter and an SAW oscillator formed on a substrate having the same temperature characteristics as those of a substrate on which the SAW filter is formed. A frequency converter includes the SAW electric part, a second local oscillation circuit, a frequency converter, a first mixer, and a second mixer. The second local oscillation circuit oscillates a second local oscillation signal using the SAW oscillator. The frequency converter converts a frequency of the second local oscillation signal to generate a first local oscillation signal. The first mixer mixes the first local oscillation signal with an input signal to output a composite signal to the SAW filter. The second mixer mixes an output from the SAW filter with the second local oscillation signal to output a frequency conversion signal.
摘要翻译：根据本发明，SAW电部件包括形成在与形成有SAW滤波器的基板相同的温度特性的基板上的SAW滤波器和SAW振荡器。变频器包括SAW电部件，第二本机振荡电路，变频器，第一混频器和第二混频器。第二本地振荡电路使用SAW振荡器振荡第二本地振荡信号。变频器转换第二本地振荡信号的频率以产生第一本地振荡信号。第一混频器将第一本地振荡信号与输入信号混合，以向SAW滤波器输出复合信号。第二混频器将来自SAW滤波器的输出与第二本地振荡信号混频以输出频率转换信号。

170. 发明授权

US5394114A One nanosecond resolution programmable waveform generator 失效
标题翻译：一纳秒分辨率可编程波形发生器
公开(公告)号：US5394114A
公开(公告)日：1995-02-28
申请号：US81955
申请日：1993-06-23
申请人： Craig M. Davis
发明人： Craig M. Davis
IPC分类号： G06F1/025 , H03K3/03 , H03K5/13 , H03K5/135 , H03L7/099 , H03L7/16 , H03K3/01 , H03L7/06
CPC分类号： G06F1/025 , H03K3/0315 , H03K5/133 , H03K5/135 , H03L7/0996 , H03L7/16
摘要： Generation of clock waveforms which have a frequency, phase offset, and duty cycle that is relative to a periodic reference signal. The outputs of a voltage controlled ring oscillator are directly applied to drive the inputs of a programmable AND, fixed OR array (PAL) to produce pulses of varied and phase offset and duty cycle. The phase offset has a resolution of one nanosecond. Additionally, the pulses generated can be ORed together within the PAL to produce clock waveforms that are multiples of the input frequency.
摘要翻译：产生具有相对于周期性参考信号的频率，相位偏移和占空比的时钟波形。电压控制环形振荡器的输出被直接应用于驱动可编程AND，固定或阵列（PAL）的输入，以产生变化和相位偏移和占空比的脉冲。相位偏移的分辨率为1纳秒。此外，所产生的脉冲可以在PAL内进行OR运算，以产生输入频率倍数的时钟波形。

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