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151. 发明授权

US06723603B2 Method of utilizing fabrication process of poly-Si spacer to build flash memory with 2bit/cell 有权
标题翻译：利用多硅衬垫制造工艺构建2bit / cell的闪速存储器的方法
公开(公告)号：US06723603B2
公开(公告)日：2004-04-20
申请号：US10183530
申请日：2002-06-28
申请人： Chien-Hung Liu , Erh-Kun Lai , Shyi Shuh Pan , Shou Wei Huang , Ying Tzoo Chen
发明人： Chien-Hung Liu , Erh-Kun Lai , Shyi Shuh Pan , Shou Wei Huang , Ying Tzoo Chen
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7887
摘要： The present invention provides a method utilizing the fabrication process of poly-Si spacers to build a flash memory with 2bit/cell. In the present invention, recessed poly-Si spacers are used to fabricate discontinuous floating gates below a control gate to build a flash memory with 2bit/cell. The present invention is characterized in that the fabrication process of poly-Si spacers is exploited to complete the fabrication process of floating gates in automatic alignment way without any extra mask process. Moreover, each memory cell in this flash memory can store two bits, hence increasing the memory capacity.
摘要翻译：本发明提供了利用多晶硅间隔物的制造工艺来构建具有2bit / cell的闪速存储器的方法。在本发明中，凹入的多晶硅间隔物用于制造控制栅极下面的不连续的浮动栅极以构建具有2bit / cell的闪速存储器。本发明的特征在于，多晶硅间隔物的制造工艺被利用以完全以自动对准方式完成浮栅的制造工艺，而无需任何额外的掩模工艺。此外，该闪速存储器中的每个存储单元可以存储两个位，从而增加存储器容量。

152. 发明授权

US06670672B1 Structure of discrete NROM cell 有权
标题翻译：离散NROM单元的结构
公开(公告)号：US06670672B1
公开(公告)日：2003-12-30
申请号：US10175839
申请日：2002-06-21
申请人： Kent Kuohua Chang , Erh-Kun Lai
发明人： Kent Kuohua Chang , Erh-Kun Lai
IPC分类号： H01L29792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： A discrete NROM cell, at least comprising: a substrate; a first ON stacking gate and a second ON stacking gate over the substrate, wherein the ON stacking gate is a structure having a nitride layer over a bottom oxide layer; an oxide layer formed over the substrate covering the first and second ON stacking gate; a polysilicon layer formed over the oxide layer; and the source/drain implanted in the substrate and next to the ON stacking gates. The structure of discrete NROM cell of the invention can solve the problem of the electrons being trapped in the nitride layer of NROM cell, and also control the source/drain implant and ON structure at precisely symmetrical positions.
摘要翻译：一个离散的NROM电池，至少包括：一个衬底; 在所述衬底上的第一ON堆叠栅极和第二ON堆叠栅极，其中所述ON堆叠栅极是在底部氧化物层上方具有氮化物层的结构; 形成在所述基板上的覆盖所述第一和第二ON堆叠栅极的氧化物层; 形成在所述氧化物层上的多晶硅层; 并且注入到衬底中并且靠近ON堆叠栅极的源极/漏极。本发明的离散NROM电池的结构可以解决电子被捕获在NROM电池的氮化物层中的问题，并且还可以在精确对称的位置控制源极/漏极注入和ON结构。

153. 发明授权

US06413815B1 Method of forming a MIM capacitor 有权
标题翻译：形成MIM电容器的方法
公开(公告)号：US06413815B1
公开(公告)日：2002-07-02
申请号：US09682069
申请日：2001-07-17
申请人： Erh-Kun Lai , Shyi-Shuh Pan , Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen
发明人： Erh-Kun Lai , Shyi-Shuh Pan , Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen
IPC分类号： H01L218242
CPC分类号： H01L21/76808 , H01L23/5223 , H01L23/53238 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A method of simultaneously forming a dual damascence runner and a metal-insulator-metal (MIM) capacitor on a semiconductor wafer. The semiconductor wafer has a first dielectric layer, which has at least a first conductive layer and at least a bottom electrode of the MIM capacitor. The surfaces of the first conductive layer and the bottom electrode of the MIM capacitor are covered with a barrier layer. A second dielectric layer, a stop layer and a third dielectric layer are formed on the surface of the barrier layer and form a sandwiched structure. A first photoresist layer is formed and the third dielectric layer is anisotropically etched down to the stop layer, thus forming a trench and an opening in the third dielectric layer above the conductive layer and the bottom electrode of the MIM capacitor. A second photoresist layer is formed and the stop layer and the second dielectric layer are etched at a bottom of the opening down to the surface of the barrier layer so as to form an opening of the top electrode. A third photoresist layer is formed and the stop layer, the second dielectric layer and the barrier layer are etched through the contact opening down to the surface of the first conductive layer so as to form a contact hole.
摘要翻译：一种在半导体晶片上同时形成双重阻力流道和金属 - 绝缘体 - 金属（MIM）电容器的方法。半导体晶片具有至少具有MIM电容器的第一导电层和至少底部电极的第一电介质层。 MIM电容器的第一导电层和底部电极的表面被阻挡层覆盖。在阻挡层的表面上形成第二电介质层，阻挡层和第三电介质层，并形成夹层结构。形成第一光致抗蚀剂层，并且将第三介电层各向异性地向下蚀刻到停止层，从而在MIM电容器的导电层和底部电极上方的第三介电层中形成沟槽和开口。形成第二光致抗蚀剂层，并且将阻止层和第二介电层在开口的底部蚀刻到阻挡层的表面，以形成顶部电极的开口。形成第三光致抗蚀剂层，并且通过接触开口将停止层，第二介电层和阻挡层蚀刻到第一导电层的表面，以形成接触孔。

154. 发明授权

US06383903B1 Method for forming the partial salicide 有权
标题翻译：形成部分自对准硅胶的方法
公开(公告)号：US06383903B1
公开(公告)日：2002-05-07
申请号：US09918638
申请日：2001-08-01
申请人： Erh-Kun Lai , Hsin-Huei Chen , Ying-Tso Chen , Shou-Wei Hwang , Yu-Ping Huang
发明人： Erh-Kun Lai , Hsin-Huei Chen , Ying-Tso Chen , Shou-Wei Hwang , Yu-Ping Huang
IPC分类号： H01L213205
CPC分类号： H01L27/105 , H01L21/823418 , H01L21/823443 , H01L27/1052
摘要： This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses an oxide layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.
摘要翻译：本发明涉及一种形成硅化物的方法，更具体地说涉及在部分区域中形成硅化物的方法。本发明使用氧化物层作为掩模层，在逻辑电路的部分区域中形成硅化物。硅化物形成在栅极上并且不形成在电池阵列区域中的扩散区域中。硅化物形成在栅极和位于周边区域的扩散区域中。本发明的方法可以使半导体器件获得较低的电阻并降低漏电缺陷。

155. 发明授权

US06355539B1 Method for forming shallow trench isolation 有权
标题翻译：形成浅沟槽隔离的方法
公开(公告)号：US06355539B1
公开(公告)日：2002-03-12
申请号：US09849245
申请日：2001-05-07
申请人： Erh-Kun Lai , Shou-Wei Huang , Yu-Ping Huang
发明人： Erh-Kun Lai , Shou-Wei Huang , Yu-Ping Huang
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A method for forming a shallow trench isolation is disclosed. The method avoids using any silicon nitride material to prevent the kooi effect and use spacers to protect the corner portions of the STI. A conductive layer is used to replace the conventional used silicon nitride layer in the formation of conventional STI regions. The invention also uses a dielectric layer comprising a pad oxide layer as a sacrificial oxide layer so that an additional sacrificial oxide layer is no longer needed. The conductive layer will be oxidized together with the substrate in the formation of the gate oxide layer so that the isolation quality will not be degraded.
摘要翻译：公开了一种用于形成浅沟槽隔离的方法。该方法避免使用任何氮化硅材料来防止kooi效应并使用间隔物来保护STI的拐角部分。在传统的STI区域的形成中，使用导电层代替常规使用的氮化硅层。本发明还使用包括衬垫氧化物层作为牺牲氧化物层的电介质层，使得不再需要额外的牺牲氧化物层。在形成栅极氧化物层时，导电层将与衬底一起被氧化，使得隔离质量不会降低。

156. 发明授权

US09019771B2 Dielectric charge trapping memory cells with redundancy 有权
标题翻译：介质电荷捕获具有冗余的存储单元
公开(公告)号：US09019771B2
公开(公告)日：2015-04-28
申请号：US13661723
申请日：2012-10-26
申请人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee
发明人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee
IPC分类号： G11C16/06 , G11C16/04 , G11C16/10
CPC分类号： G11C16/0475 , G11C16/10
摘要： A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.
摘要翻译：介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

157. 发明授权

US08426294B2 3D memory array arranged for FN tunneling program and erase 有权
标题翻译： 3D存储阵列用于FN隧道编程和擦除
公开(公告)号：US08426294B2
公开(公告)日：2013-04-23
申请号：US13476964
申请日：2012-05-21
申请人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Hang-Ting Lue
发明人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Hang-Ting Lue
IPC分类号： H01L29/76
CPC分类号： G11C16/0458 , H01L27/0688 , H01L27/10 , H01L27/11578 , H01L27/11582
摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.
摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。该设备可以作为3D和解码的闪存操作。

158. 发明授权

US08395935B2 Cross-point self-aligned reduced cell size phase change memory 有权
标题翻译：交叉点自对准减小单元尺寸相变存储器
公开(公告)号：US08395935B2
公开(公告)日：2013-03-12
申请号：US12899232
申请日：2010-10-06
申请人： Hsiang-Lan Lung , Erh-Kun Lai
发明人： Hsiang-Lan Lung , Erh-Kun Lai
IPC分类号： G11C11/00
CPC分类号： H01L27/2436 , G11C13/0004 , H01L27/10 , H01L27/105
摘要： A programmable memory array is disclosed in which the phase change memory cells are self-aligned at the access devices and at the cross-points of the bit lines and the word lines. A method for making the array employs one line mask to define the bit lines and another line mask to define the word lines. The front end of line (FEOL) memory cell elements are in the same layer as the polysilicon gates. The bit lines and the word lines intersect over the devices, and the memory cell elements are formed at the intersections of the bit lines and the word line.
摘要翻译：公开了一种可编程存储器阵列，其中相位存储器单元在访问设备和位线和字线的交叉点处是自对准的。用于制作阵列的方法使用一个线掩模来定义位线和另一个线掩模来定义字线。行前端（FEOL）存储单元元件与多晶硅栅极处于同一层。位线和字线在器件上相交，并且存储器单元元件形成在位线和字线的交点处。

159. 发明授权

US08237144B2 Polysilicon plug bipolar transistor for phase change memory 有权
标题翻译：用于相变存储器的多晶硅插头双极晶体管
公开(公告)号：US08237144B2
公开(公告)日：2012-08-07
申请号：US13252152
申请日：2011-10-03
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung H. Lam
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung H. Lam
IPC分类号： H01L29/02
CPC分类号： H01L45/04 , G11C13/0004 , H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.
摘要翻译：本文描述了存储器件和制造方法。本文描述的存储器件包括多个存储器单元。多个存储单元中的存储单元包括相应的双极结型晶体管和存储元件。双极结晶体管被布置成共同的集电极配置，并且包括发射器，其包括具有第一导电类型的掺杂多晶硅，发射极接触多个字线中的对应字线以限定pn结。双极结晶体管包括作为基极的发射极下面的相应字线的一部分，以及包含基底下方的单晶衬底的一部分的集电极。

160. 发明授权

US08183617B2 Injection method with Schottky source/drain 有权
标题翻译：肖特基源/漏极注入法
公开(公告)号：US08183617B2
公开(公告)日：2012-05-22
申请号：US12430817
申请日：2009-04-27
申请人： Yi-Hsuan Hsiao , Erh-Kun Lai , Hang-Ting Lue
发明人： Yi-Hsuan Hsiao , Erh-Kun Lai , Hang-Ting Lue
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , G11C16/0408 , H01L21/28282 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.
摘要翻译：描述了具有肖特基源和漏极的非易失性存储单元的注入方法。载流子注入效率由硅化物和硅的界面特性控制。通过控制栅极和源极/漏极的重叠以及通过控制注入，激活和/或栅极过程来修改肖特基势垒。

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