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    • 153. 发明申请
    • Semiconductor laser apparatus and fabrication method thereof
    • 半导体激光装置及其制造方法
    • US20050220159A1
    • 2005-10-06
    • US11092947
    • 2005-03-30
    • Yasuyuki BesshoMasayuki HataDaijiro InoueTsutomu Yamaguchi
    • Yasuyuki BesshoMasayuki HataDaijiro InoueTsutomu Yamaguchi
    • H01S5/40H01L29/00H01S5/022
    • H01S5/4025H01L2224/32245H01L2224/48463H01L2224/73265H01S5/4087
    • A blue-violet semiconductor laser device has a first p-electrode formed on its upper surface and a first n-electrode formed on its lower surface. A red semiconductor laser device has a second n-electrode formed on its upper surface and a second p-electrode formed on its lower surface. An infrared semiconductor laser device has a third n-electrode formed on its upper surface and a third p-electrode formed on its lower surface. Solder films are partially formed on the upper surface of the first p-electrode in the blue-violet semiconductor laser device. Two of the solder films are formed with a predetermined distance between them on the upper surface of the first p-electrode. This results in a portion of the first p-electrode being exposed. The first, second and third p-electrodes of the blue-violet semiconductor laser device, red semiconductor laser device, and infrared semiconductor laser device are common electrodes.
    • 蓝紫色半导体激光器件具有在其上表面上形成的第一p电极和形成在其下表面上的第一n电极。 红色半导体激光器件具有在其上表面上形成的第二n电极和形成在其下表面上的第二p电极。 红外半导体激光器件具有在其上表面上形成的第三n电极和形成在其下表面上的第三p电极。 在蓝紫色半导体激光器件中的第一p电极的上表面部分地形成焊料膜。 两个焊料膜在第一p电极的上表面之间以它们之间的预定距离形成。 这导致第一p电极的一部分被暴露。 蓝紫色半导体激光器件的第一,第二和第三p电极,红色半导体激光器件和红外半导体激光器件是公共电极。
    • 158. 发明授权
    • Memory apparatus and method capable of setting attribute of information
to be cached
    • 能够设置要缓存的信息的属性的存储装置和方法
    • US5553262A
    • 1996-09-03
    • US231963
    • 1994-04-22
    • Itsuko IshidaMasayuki HataTatsuo Yamada
    • Itsuko IshidaMasayuki HataTatsuo Yamada
    • G06F12/08G06F12/12
    • G06F12/0848G06F12/0846G06F12/0864G06F12/0842G06F12/127G06F2212/601
    • A cache memory apparatus allocates memory regions on the basis of information attributes. The required memory region corresponding to the attribute is accessed before caching is implemented. This enables considerable reduction in apparatus that would otherwise be required to be duplicated among different chips corresponding to the number of information attributes. In a multiple data processing implementation, cache memory regions are allocated for each data processor. The required memory regions of the cache memory are accessed in accordance with information specifying the data processor before caching is carried out. To avoid data collision when the main memory data is substantially rewritten, and when data having the same address and different access types exist simultaneously, data representing the type of access is stored. In response to a change in access, all data signals stored in each ways is nullified so that a plurality of data stored in the memory regions is not simultaneously output.
    • 高速缓存存储装置根据信息属性分配存储区域。 在实现缓存之前访问对应于该属性的所需存储区域。 这使得能够显着地减少否则将需要在对应于信息属性的数量的不同芯片之间复制的装置。 在多重数据处理实现中,为每个数据处理器分配高速缓冲存储器区域。 根据在执行缓存之前指定数据处理器的信息来访问高速缓冲存储器的所需存储区域。 为了在主存储器数据被重写时避免数据冲突,并且当具有相同地址和不同访问类型的数据同时存在时,存储表示访问类型的数据。 响应于访问的变化,以各种方式存储的所有数据信号无效,使得存储在存储器区域中的多个数据不被同时输出。
    • 159. 发明授权
    • Data access apparatus for preventing further cache access in case of an
error during block data transfer
    • 数据访问装置,用于在块数据传输期间发生错误时防止进一步的高速缓存访​​问
    • US5544341A
    • 1996-08-06
    • US454893
    • 1995-05-31
    • Hiromasa NakagawaAkira YamadaMasayuki Hata
    • Hiromasa NakagawaAkira YamadaMasayuki Hata
    • G06F12/08G11C29/00G06F13/00G06F11/00
    • G11C29/88G06F12/0879
    • A data processor and method for preventing access to a cache memory when an abnormality occurs during a block data transfer. The data processor is provided with a central processing unit (CPU), a memory and the cache which stores a part of the data being stored in the memory. When the data to be accessed by the central processing unit is not stored in the cache, the data processor employs a block transfer method where the central processing unit reads out from the memory a block of data, including a predetermined number of data (words) in which the data to be accessed is located. When an abnormality, such as a parity error, is detected in transferring a data word in the block of data to be accessed, the cache is inhibited from reading another data word in the block to be accessed, and the CPU stops reading out the rest of the block of data to be read out from the memory, so that the central processing unit can immediately take action to respond to the abnormality.
    • 一种用于在块数据传送期间发生异常时防止对高速缓存存储器的访问的数据处理器和方法。 数据处理器设置有中央处理单元(CPU),存储器和存储存储在存储器中的一部分数据的高速缓存。 当中央处理单元要访问的数据不存储在高速缓存中时,数据处理器采用块传送方法,其中中央处理单元从存储器读出包括预定数量的数据(字)的数据块, 其中要访问的数据位于其中。 当在传送要访问的数据块中的数据字中检测到诸如奇偶校验错误的异常时,禁止高速缓存读取要访问的块中的另一个数据字,并且CPU停止读出其余部分 的数据块从存储器读出,使得中央处理单元可以立即采取动作来响应异常。