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141. 发明申请

US20080079455A1 IC Chip Package, Test Equipment and Interface for Performing a Functional Test of a Chip Contained Within Said Chip Package 审中-公开
标题翻译： IC芯片封装，用于执行所述芯片封装内包含的芯片的功能测试的测试设备和接口
公开(公告)号：US20080079455A1
公开(公告)日：2008-04-03
申请号：US11866677
申请日：2007-10-03
申请人： Joerg Vollrath , Marcin Gnat , Ralf Schneider
发明人： Joerg Vollrath , Marcin Gnat , Ralf Schneider
IPC分类号： G01R31/26
CPC分类号： G11C29/56 , G01R1/07 , G01R31/2889 , G01R31/318533 , G01R31/31905 , G11C29/48 , G11C2029/5602 , H01L2224/4824
摘要： An interface between a test access port of an integrated circuit chip and a test equipment, which is designed to perform a functional test of the chip, is provided. The interface includes electric pads on either sides of the chip and the test equipment. The pads are arranged to interact by means of capacitive coupling, when a test data signal is input to one of the pads. Preferably, both pads are connected with either a receiver or a driver depending on the direction of the data flow. The electric pads relating to the chip's side may be arranged within the wiring substrate of a chip package, particularly along edge portion of the substrate, which encompasses an inner portion of the substrate, in which a ball-grid-array can be formed.
摘要翻译：提供集成电路芯片的测试访问端口和被设计用于执行芯片的功能测试的测试设备之间的接口。接口包括芯片两侧的电焊盘和测试设备。当测试数据信号被输入到其中一个焊盘时，焊盘被布置成通过电容耦合相互作用。优选地，两个焊盘根据数据流的方向与接收器或驱动器连接。与芯片侧相关的电焊盘可以布置在芯片封装的布线基板内，特别是沿着基板的边缘部分，其包围可以形成球栅阵列的基板的内部。

142. 发明授权

US07346784B1 Integrated circuit device programming with partial power 有权
标题翻译：具有部分功率的集成电路器件编程
公开(公告)号：US07346784B1
公开(公告)日：2008-03-18
申请号：US10231694
申请日：2002-08-29
申请人： Conrad A. Theron
发明人： Conrad A. Theron
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： H03K19/17748 , G01R31/318516 , G11C5/147 , G11C29/12005 , G11C29/48 , H03K19/17736 , H03K19/17784 , H05K1/029 , H05K2201/10053 , H05K2201/10159 , H05K2201/10212 , H05K2201/10689
摘要： A separate program power input is provided to a programmable logic array's memory to permit it to be programmed independently of printed circuit board power. Means are provided to isolate the program power input from the array's programmable logic circuit. Means are further provided to isolate the memory from the programmable logic circuit. The program power is not connected directly or indirectly to the programmable logic circuit thereby permitting the use of low-power devices to program the memory without connecting the printed circuit board to a power supply.
摘要翻译：单独的程序电源输入提供给可编程逻辑阵列的存储器，以允许其独立于印刷电路板电源进行编程。提供了用于隔离阵列可编程逻辑电路的程序电源输入的装置。还提供了用于将存储器与可编程逻辑电路隔离的装置。程序电源不直接或间接连接到可编程逻辑电路，从而允许使用低功率器件对存储器进行编程，而不将印刷电路板连接到电源。

143. 发明授权

US07345518B2 Digital storage element with dual behavior 有权
标题翻译：具有双重行为的数字存储元件
公开(公告)号：US07345518B2
公开(公告)日：2008-03-18
申请号：US11171612
申请日：2005-06-30
申请人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah , James R. Hochschild
发明人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah , James R. Hochschild
IPC分类号： H03K3/289
CPC分类号： G11C29/32 , G01R31/318552 , G01R31/318575 , G01R31/31858 , G11C29/48 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The master and slave transparent latches have opposite transparent polarities when in a functional mode and have the same polarities (e.g., positive level sense) when in a scan mode. The transparent polarity of a transparent latch defines the state of a clock to that latch for which the transparent latch is transparent.
摘要翻译：数字存储元件包括主透明锁存器，其从数据输入端口接收功能数据，并从耦合到主透明锁存器的扫描输入端口和从属透明锁存器扫描数据。从机透明锁存器包括专用功能数据和扫描数据输出端口。当处于扫描模式时，主功能模式和从属透明锁存器在功能模式下具有相反的透明极性，并具有相同的极性（例如，正电平感测）。透明锁定器的透明极性限定了透明闩锁为透明闩锁的锁存器的时钟状态。

144. 发明申请

US20080061811A1 Electronic device having an interface supported testing mode 有权
公开(公告)号：US20080061811A1
公开(公告)日：2008-03-13
申请号：US11981854
申请日：2007-10-31
申请人： Adrian Ong
发明人： Adrian Ong
IPC分类号： G01R31/26
CPC分类号： G01R31/318513 , G01R31/31701 , G01R31/3172 , G01R31/31723 , G01R31/319 , G11C29/1201 , G11C29/48 , G11C2029/0401 , H01L2224/05554 , H01L2224/48139
摘要： A system is provided for testing a logic device and an integrated circuit disposed within a semiconductor device package. The logic device may be configured to operate in at least a normal mode and a test mode. A terminal external to the semiconductor device package may be electronically coupled to the logic device and the integrated circuit. The terminal may be configured to operate as a shared input for the logic device and the integrated circuit. A multiplexer circuit may be configured to convey a first signal from the terminal to the logic device in the test mode, to convey a second signal from the integrated circuit to the logic device in the normal mode, and to receive a third signal from the integrated circuit for causing a transition between the normal mode and the test mode.

145. 发明申请

US20080059103A1 System and Method for Implementing a Programmable DMA Master With Date Checking Utilizing a Drone System Controller 失效
标题翻译：使用无人机系统控制器实现可编程DMA主机的日期检查的系统和方法
公开(公告)号：US20080059103A1
公开(公告)日：2008-03-06
申请号：US11470282
申请日：2006-09-06
申请人： Robert W. Berry , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
IPC分类号： G06F19/00 , G11C29/00
CPC分类号： G11C29/48 , G06F11/26
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with date checking utilizing a drone system controller. According to a preferred embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译：一种方法，系统和计算机可用介质，用于使用无人机系统控制器实现具有日期检查的可编程DMA主机。根据本发明的优选实施例，无人机处理器生成随机数据的集合，并将随机数据集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。无人机处理器将随机数据集合的第三副本写入处理器存储器。当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。

146. 发明申请

US20080056036A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20080056036A1
公开(公告)日：2008-03-06
申请号：US11824423
申请日：2007-06-29
申请人： Jong-Won Lee , Sung-Kwon Cho
发明人： Jong-Won Lee , Sung-Kwon Cho
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C11/406 , G11C11/401 , G11C11/40618 , G11C29/48 , G11C29/50 , G11C29/50012
摘要： A semiconductor memory device checks a RAS timing to recognize and set an operation timing of the semiconductor memory device. The semiconductor memory device includes an input buffer, a RAS timing controller and a bank controller. The input buffer transmits a RAS timing test signal. The RAS timing controller generates a RAS timing signal. The bank controller controls a refresh operation timing in response to an output of the input buffer in a test mode and the RAS timing signal in a normal mode.
摘要翻译：半导体存储器件检查RAS定时以识别并设置半导体存储器件的操作定时。半导体存储器件包括输入缓冲器，RAS定时控制器和存储体控制器。输入缓冲器发送RAS定时测试信号。 RAS定时控制器产生RAS定时信号。银行控制器响应于测试模式下的输入缓冲器的输出和正常模式下的RAS定时信号来控制刷新操作定时。

147. 发明授权

US07336558B2 Semiconductor memory device with reduced number of pads 有权
标题翻译：具有减少焊盘数量的半导体存储器件
公开(公告)号：US07336558B2
公开(公告)日：2008-02-26
申请号：US11264512
申请日：2005-10-31
申请人： Woo-Seop Jeong
发明人： Woo-Seop Jeong
IPC分类号： G11C8/00
CPC分类号： G11C29/1201 , G11C5/066 , G11C29/48
摘要： A semiconductor memory device is provided which comprises a group of address pads and an input circuit configured to receive a first address from the address pads at a first transition of an external clock signal and a second address from the address pads at a second transition of the external clock signal.
摘要翻译：提供了一种半导体存储器件，其包括一组地址焊盘和一个输入电路，该输入电路被配置为在外部时钟信号的第一转变处接收来自地址焊盘的第一地址，并且在第二转换时从地址焊盘接收第二地址外部时钟信号。

148. 发明授权

US07327766B2 Circuit configuration for receiving a data signal 有权
标题翻译：用于接收数据信号的电路配置
公开(公告)号：US07327766B2
公开(公告)日：2008-02-05
申请号：US10247577
申请日：2002-09-19
申请人： Reidar Stief
发明人： Reidar Stief
IPC分类号： H04J3/02
CPC分类号： G11C29/12015 , G11C7/1051 , G11C7/1066 , G11C11/401 , G11C29/48 , G11C2207/107
摘要： In a clock-synchronously operated semiconductor memory, particularly a DDR SDRAM, data are read in clock-synchronously with respect to a data strobe signal in the normal mode, according to standard. During the test mode, a DQ receiver is supplied with the operating clock signal instead of the DQS signal. A downstream memory element is bridged by a direct signal path. To change over, multiplexers/demultiplexers driven by the test mode control signal are provided. The data signal supplied to the memory cell array is available immediately after a write command has been applied to the memory cell array.
摘要翻译：在时钟同步操作的半导体存储器中，特别是DDR SDRAM中，根据标准，在正常模式下，以数据选通信号的时钟同步方式读取数据。在测试模式期间，DQ接收机被提供有操作时钟信号而不是DQS信号。下游存储器元件由直接信号路径桥接。为了切换，提供由测试模式控制信号驱动的多路复用器/解复用器。在将写入命令应用于存储单元阵列之后，提供给存储单元阵列的数据信号立即可用。

149. 发明申请

US20080028104A1 Semiconductor device and operation control method of semiconductor device 审中-公开
标题翻译：半导体器件的半导体器件和操作控制方法
公开(公告)号：US20080028104A1
公开(公告)日：2008-01-31
申请号：US11808675
申请日：2007-06-12
申请人： Kiyoshi Tsuneki
发明人： Kiyoshi Tsuneki
IPC分类号： G06F3/00
CPC分类号： G11C29/48 , G11C5/04 , G11C29/1201 , H01L25/18 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311
摘要： A semiconductor device according to an embodiment of the present invention includes: a first semiconductor chip performing a predetermined operation based on a first control signal or a second control signal; a second semiconductor chip selectively outputting the external first control signal or the internal second control signal; and a line inputting the first or second control signal output from the second semiconductor chip to the first semiconductor chip.
摘要翻译：根据本发明实施例的半导体器件包括：基于第一控制信号或第二控制信号执行预定操作的第一半导体芯片; 选择性地输出外部第一控制信号或内部第二控制信号的第二半导体芯片; 以及将从第二半导体芯片输出的第一或第二控制信号输入到第一半导体芯片的线。

150. 发明申请

US20080016417A1 Cell Supporting Scan-based Tests and With Reduced Time Delay in Functional Mode 有权
标题翻译：支持基于扫描的测试，并在功能模式下减少时间延迟
公开(公告)号：US20080016417A1
公开(公告)日：2008-01-17
申请号：US11309191
申请日：2006-07-12
申请人： Sanchayan Sinha , Dharin N. Shah , Achin Grover
发明人： Sanchayan Sinha , Dharin N. Shah , Achin Grover
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/48 , G01R31/31858 , G01R31/318594 , G11C2029/3202
摘要： A memory cell supporting scan-based tests and with reduced time delay in functional mode. The memory cell generates separate clocks for latching functional and scan data into a storage element contained in the memory cell. The use of separate clock signals permits transmission of scan data and functional data via separate paths, thereby eliminating additional circuitry that are otherwise needed to multiplex such scan and functional data through a same path. The absence of such additional circuitry reduces the time delays from input to output. The structure of the memory cell provided also permits easy addition of logic functions without substantially affecting operating speeds.
摘要翻译：支持基于扫描的测试和功能模式下延时缩短的存储单元。存储器单元产生用于将功能和扫描数据锁定到存储单元中所包含的存储元件的单独时钟。使用单独的时钟信号允许通过分离的路径传输扫描数据和功能数据，从而消除另外需要通过相同路径复用这种扫描和功能数据的附加电路。没有这样的附加电路减少了从输入到输出的时间延迟。所提供的存储单元的结构也允许容易地添加逻辑功能而基本上不影响操作速度。

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