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141. 发明申请

US20120144356A1 ANALYZING MULTIPLE INDUCED SYSTEMATIC AND STATISTICAL LAYOUT DEPENDENT EFFECTS ON CIRCUIT PERFORMANCE 失效
标题翻译：分析多种诱导系统和统计布局对电路性能的依赖性影响
公开(公告)号：US20120144356A1
公开(公告)日：2012-06-07
申请号：US13371537
申请日：2012-02-13
申请人： Shayak Banerjee , Dureseti Chidambarrao , James A. Culp , Praveen Elakkumanan , Saibal Mukhopadhyay
发明人： Shayak Banerjee , Dureseti Chidambarrao , James A. Culp , Praveen Elakkumanan , Saibal Mukhopadhyay
IPC分类号： G06F9/455
CPC分类号： G06F17/5009 , G06F2217/10
摘要： A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.
摘要翻译：一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

142. 发明申请

US20110272779A1 EFUSE CONTAINING SIGE STACK 有权
标题翻译： EFUSE包含信号堆栈
公开(公告)号：US20110272779A1
公开(公告)日：2011-11-10
申请号：US13189016
申请日：2011-07-22
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

143. 发明授权

US08053844B2 Hybrid orientation scheme for standard orthogonal circuits 失效
标题翻译：标准正交电路的混合定向方案
公开(公告)号：US08053844B2
公开(公告)日：2011-11-08
申请号：US12431094
申请日：2009-04-28
申请人： Dureseti Chidambarrao
发明人： Dureseti Chidambarrao
IPC分类号： H01L29/04 , H01L21/77 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/6659 , H01L29/7842
摘要： Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate, comprising first areas having a first crystalline orientation and second areas having a second crystalline orientation. The first crystalline orientation of the first areas is not parallel or perpendicular to the second crystalline orientation of the second areas. The integrated circuit further comprises first type devices on the first areas and second type devices on the second areas, wherein the first type devices are parallel or perpendicular to the second type devices. Specifically, the first type devices comprise p-type field effect transistors (PFETs) and the second type devices comprise n-type field effect transistors (NFETs).
摘要翻译：本文的实施例用于标准正交电路的混合取向方案的装置，方法等。本发明的实施例的集成电路包括混合取向衬底，其包括具有第一结晶取向的第一区域和具有第二结晶取向的第二区域。第一区域的第一晶体取向不平行或垂直于第二区域的第二晶体取向。集成电路还包括第一区域上的第一类型设备和第二区域上的第二类型设备，其中第一类型设备平行或垂直于第二类型设备。具体地，第一类型器件包括p型场效应晶体管（PFET），第二类型器件包括n型场效应晶体管（NFET）。

144. 发明授权

US07979815B2 Compact model methodology for PC landing pad lithographic rounding impact on device performance 有权
标题翻译： PC着陆垫光刻圆形的紧凑型模型方法对设备性能的影响
公开(公告)号：US07979815B2
公开(公告)日：2011-07-12
申请号：US11970990
申请日：2008-01-08
申请人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5036
摘要： A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.
摘要翻译：一种用于对具有有源器件区域，栅极结构并且包括连接到栅极结构并且设置在有源器件区域上方的导线特征来建模半导体晶体管器件结构的方法和计算机程序产品，所述导电线特征包括导电层衬垫特征设置在待建模的电路中的有源器件区域的边缘附近。该方法包括确定由着陆焊盘特征限定的边缘与有源器件区域的边缘之间的距离，以及通过建模着陆焊盘特征的光刻圆整效应，确定作为功能的有源器件区域的宽度变化由着陆垫特征限定的边缘到活动设备区域的边缘之间的距离。根据这些数据，有源器件区域宽度（deltaW加法器）的有效变化与确定的距离有关。

145. 发明授权

US07964865B2 Strained silicon on relaxed sige film with uniform misfit dislocation density 有权
标题翻译：应变硅在轻松的超薄膜上具有均匀的失配位错密度
公开(公告)号：US07964865B2
公开(公告)日：2011-06-21
申请号：US11048739
申请日：2005-02-03
申请人： Dureseti Chidambarrao , Omer H. Dokumaci
发明人： Dureseti Chidambarrao , Omer H. Dokumaci
IPC分类号： H01L29/06
CPC分类号： H01L21/26506 , H01L21/324 , H01L29/1054
摘要： A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained SiGe layer. During the annealing, interstitial dislocation loops are formed as uniformly distributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.
摘要翻译：提供一种形成半导体衬底结构的方法。在硅衬底上形成压缩应变SiGe层。原子被离子注入SiGe层以造成范围内的损伤。进行退火以松弛应变的SiGe层。在退火过程中，间隙位错环形成均匀分布在SiGe层中。间隙位错环为SiGe层和硅衬底之间的失配位错的成核提供了基础。由于间隙位错环分布均匀，因此错位位置也均匀分布，从而松弛SiGe层。在松弛的SiGe层上形成拉伸应变硅层。

146. 发明授权

US07943493B2 Electrical fuse having a fully silicided fuselink and enhanced flux divergence 有权
标题翻译：电熔丝具有完全硅化的富熔体和增强的焊剂分散
公开(公告)号：US07943493B2
公开(公告)日：2011-05-17
申请号：US12873882
申请日：2010-09-01
申请人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/20
CPC分类号： H01L23/5256 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
摘要翻译：在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

147. 发明授权

US07928571B2 Device having dual etch stop liner and reformed silicide layer and related methods 有权
标题翻译：具有双蚀刻停止衬垫和重整硅化物层的器件及相关方法
公开(公告)号：US07928571B2
公开(公告)日：2011-04-19
申请号：US11850968
申请日：2007-09-06
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
IPC分类号： H01L27/088 , H01L29/40 , H01L23/48 , H01L23/52 , H01L23/62
CPC分类号： H01L29/7842 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823864 , H01L29/7843
摘要： The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.
摘要翻译：本发明提供一种具有双重氮化硅衬垫和重整硅化物层的半导体器件以及用于制造这种器件的相关方法。重整的硅化物层具有与未暴露于形成双重氮化硅衬里的硅化物层基本相似的厚度和电阻。本发明的第一方面提供一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到硅化物层，去除第一氮化硅衬垫的一部分，重整硅化物层的一部分在去除步骤期间去除，并且将第二氮化硅衬垫施加到硅化物层。

148. 发明申请

US20100330783A1 ELECTRICAL FUSE HAVING A FULLY SILICIDED FUSELINK AND ENHANCED FLUX DIVERGENCE 有权
标题翻译：全自动充电式电熔炉和增强型流量分流器
公开(公告)号：US20100330783A1
公开(公告)日：2010-12-30
申请号：US12873882
申请日：2010-09-01
申请人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/20
CPC分类号： H01L23/5256 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
摘要翻译：在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

149. 发明申请

US20100127327A1 GATE ELECTRODE STRESS CONTROL FOR FINFET PERFORMANCE ENHANCEMENT DESCRIPTION 有权
标题翻译：用于FINFET性能增强的门电极应力控制
公开(公告)号：US20100127327A1
公开(公告)日：2010-05-27
申请号：US12695660
申请日：2010-01-28
申请人： Dureseti Chidambarrao
发明人： Dureseti Chidambarrao
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66795 , H01L29/7842 , H01L29/78684
摘要： A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.
摘要翻译： finFET及其制造方法包括形成在半导体鳍片的沟道区域上的栅电极。半导体鳍具有晶体取向和轴向特定的压阻系数。形成栅电极，该固有应力确定为影响并优选地优化沟道区内的载流子迁移率。为此，固有应力优选地在栅极电极和半导体鳍片沟道区域内提供与轴向特定的压阻系数相匹配的感应的轴向应力。

150. 发明授权

US07691698B2 Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain 失效
标题翻译：具有嵌入式SiGe源极/漏极的假晶Si / SiGe / Si体器件
公开(公告)号：US07691698B2
公开(公告)日：2010-04-06
申请号：US11358483
申请日：2006-02-21
申请人： Dureseti Chidambarrao , Anda C. Mocuta , Dan M. Mocuta , Carl Radens
发明人： Dureseti Chidambarrao , Anda C. Mocuta , Dan M. Mocuta , Carl Radens
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及在PFET的源极/漏极区域中具有至少一个嵌入的SiGe层以及在NFET的沟道区域中至少一个嵌入的SiGe层的CMOS器件。在一个实施方案中，本发明的结构增强了NFET器件中的电子迁移率，并进一步提高了PFET器件中的空穴迁移率。此外，通过使用制造方法并因此实现本发明的最终结构，还可以在同一衬底上构造每个具有嵌入的SiGe层的PFET和NFET。

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