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131. 发明授权

US06013948A Stackable chip scale semiconductor package with mating contacts on opposed surfaces 失效
标题翻译：可堆叠的芯片级半导体封装，在相对的表面上具有配合触点
公开(公告)号：US06013948A
公开(公告)日：2000-01-11
申请号：US53274
申请日：1998-04-01
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01L23/13 , H01L23/14 , H01L23/31 , H01L23/498 , H01L25/10 , H01L23/50 , H01L23/12 , H01L23/36 , H05K1/18
CPC分类号： H01L23/147 , H01L23/13 , H01L23/3114 , H01L23/49816 , H01L23/49883 , H01L24/97 , H01L25/105 , H01L2224/0401 , H01L2224/05599 , H01L2224/06136 , H01L2224/16225 , H01L2224/16237 , H01L2224/48091 , H01L2224/4824 , H01L2224/8114 , H01L2224/85399 , H01L2224/97 , H01L2225/1058 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12044 , H01L2924/15153 , H01L2924/15156 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18165
摘要： A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second contacts formed on an opposing second surface of the substrate. Conductive vias in the substrate electrically connect the first contacts to the second contacts. In addition, the first contacts and the second contacts have a mating configuration, such that a second package can be stacked on and electrically connected to the package. The method for fabricating the package includes the steps of: laser machining and etching the vias, forming an insulating layer in the vias, and then depositing a conductive material within the vias.
摘要翻译：提供了可堆叠的芯片级半导体封装和制造封装的方法。该封装包括具有安装半导体管芯的管芯安装部位的基板。封装还包括形成在衬底的第一表面上的第一触点，以及形成在衬底的相对的第二表面上的第二触点。衬底中的导电通孔将第一触头电连接到第二触点。此外，第一触点和第二触点具有配合构造，使得第二封装可以堆叠在封装上并与其电连接。制造封装的方法包括以下步骤：激光加工和蚀刻通孔，在通孔中形成绝缘层，然后在导电孔内沉积导电材料。

132. 发明授权

US5990566A High density semiconductor package 失效
标题翻译：高密度半导体封装
公开(公告)号：US5990566A
公开(公告)日：1999-11-23
申请号：US82093
申请日：1998-05-20
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood , Mike Brooks , Eugene Cloud
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood , Mike Brooks , Eugene Cloud
IPC分类号： H01L23/48 , H01L23/498 , H01L25/065 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L23/4985 , H01L24/72 , H01L2225/0652 , H01L2225/06551 , H01L2225/06575 , H01L2225/06579 , H01L2924/01004 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/351
摘要： A semiconductor package and a method of fabrication are provided. The package includes multiple semiconductor dice contained in a housing, and mounted on edge to a substrate. Each die includes a polymer interconnect which attaches to a face of the die, and wraps around an end (or side) of the die. The polymer interconnect includes a flexible polymer tape with patterns of conductors. The conductors include microbumps for bonding to the die bond pads, and edge contacts for electrical connection to mating contacts on the substrate. The package also includes a force applying mechanism for biasing the dice against the substrate. In alternate embodiments, the polymer interconnect includes resilient edge contacts, cantilevered edge contacts, or multi level edge contacts.
摘要翻译：提供半导体封装和制造方法。封装包括容纳在外壳中的多个半导体裸片，并且安装在边缘到基板上。每个管芯包括连接到管芯的表面并且围绕管芯的端部（或侧面）的聚合物互连。聚合物互连包括具有导体图案的柔性聚合物带。导体包括用于与芯片接合焊盘接合的微胶片，以及用于与衬底上的配合触点电连接的边缘触点。该包装还包括用于将骰子偏压抵靠衬底的施力机构。在替代实施例中，聚合物互连包括弹性边缘触点，悬臂边缘触点或多级边缘触点。

133. 发明授权

US5674785A Method of producing a single piece package for semiconductor die 失效
标题翻译：制造用于半导体管芯的单件封装的方法
公开(公告)号：US5674785A
公开(公告)日：1997-10-07
申请号：US563191
申请日：1995-11-27
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01L23/13 , H01L23/14 , H01L23/31 , H01L23/498 , H01L25/10 , H01L21/60
CPC分类号： H01L23/49816 , H01L23/13 , H01L23/147 , H01L23/3114 , H01L23/49883 , H01L24/97 , H01L2224/06135 , H01L2224/06136 , H01L2224/16235 , H01L2224/1624 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/4824 , H01L2224/48465 , H01L2224/73215 , H01L2224/97 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/10253 , H01L2924/15153 , H01L2924/15311 , H01L2924/18165 , Y10T29/4913 , Y10T29/49133
摘要： A method for packaging a bare semiconductor die using a one piece package body with a pattern of external conductors is provided. The package body includes a die mounting location and an interconnect opening that aligns with the bond pads on the die. Electrical interconnects, such as wire bonds, are formed through the interconnect opening to establish electrical communication between the bond pads on the die and the conductors on the package body. The conductors on the package body can include solder bumps to permit the package to be flip chip mounted to a supporting substrate such as a printed circuit board or to be mounted in a chip-on-board configuration. The package can be fabricated by bulk micro-machining silicon wafers to form the package bodies, attaching the dice to the package bodies, and then singulating the wafer. Alternately the package body can be formed of a FR-4 material. In addition, multiple dice can be attached to a package body to form a multi-chip module.
摘要翻译：提供了一种使用具有外部导体图案的单件封装体封装裸半导体管芯的方法。封装主体包括管芯安装位置和与管芯上的接合焊盘对准的互连开口。通过互连开口形成诸如引线接合的电互连，以在管芯上的接合焊盘和封装主体上的导体之间建立电连通。封装主体上的导体可以包括焊料凸块，以允许将封装倒装芯片安装到诸如印刷电路板的支撑基板上，或者以板上芯片配置安装。封装可以通过大量微加工硅晶片来制造，以形成封装体，将裸片连接到封装体，然后将晶片分离。替代地，包装体可以由FR-4材料形成。此外，多个骰子可以附接到包装体以形成多芯片模块。

134. 发明授权

US5495667A Method for forming contact pins for semiconductor dice and interconnects 失效
标题翻译：用于形成用于半导体管芯和互连的接触针的方法
公开(公告)号：US5495667A
公开(公告)日：1996-03-05
申请号：US335262
申请日：1994-11-07
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： H01L21/60 , G01R1/06 , G01R31/28 , H01L21/607 , H01L23/485 , H01L23/49 , H05K3/32 , G01R9/06
CPC分类号： H01L24/12 , G01R1/06 , G01R31/2884 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/48 , H01L24/742 , G01R31/2886 , H01L2224/0401 , H01L2224/04042 , H01L2224/05568 , H01L2224/056 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/1134 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/451 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48655 , H01L2224/48724 , H01L2224/48755 , H01L2224/48844 , H01L2224/48855 , H01L2224/742 , H01L2224/78301 , H01L24/16 , H01L24/45 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H05K3/328 , Y10T29/49149
摘要： A method for forming contact pins adapted to form an electrical connection with a mating contact location is provided. In a first embodiment, the contact pins are formed on an interconnect used for testing a semiconductor die and are adapted to establish an electrical connection with the bond pads of the die. In a second embodiment, the contact pins are formed directly on the bond pads of a die and can be used for establishing a permanent or temporary electrical connection to the pads. The contact pins include a base portion attached to the die or interconnect, a compliant spring segment, and a contact ball at the tip. The contact pins are formed using a wire bonding process or a welding process in which a metal wire is simultaneously heated and shaped into a compliant structure as it is attached to the die or interconnect.
摘要翻译：提供一种用于形成适于与配合接触位置形成电连接的接触针的方法。在第一实施例中，接触针形成在用于测试半导体管芯的互连件上，并且适于与管芯的接合焊盘建立电连接。在第二实施例中，接触销直接形成在管芯的接合焊盘上，并且可以用于建立与焊盘的永久或临时的电连接。接触销包括附接到模具或互连的基部，柔性弹簧段和尖端处的接触球。接触销使用引线接合工艺或焊接工艺形成，其中金属线同时被加热并且被成形为顺应结构，因为它附接到管芯或互连。

135. 发明授权

US07791184B2 Image sensor packages and frame structure thereof 有权
标题翻译：图像传感器封装及其框架结构
公开(公告)号：US07791184B2
公开(公告)日：2010-09-07
申请号：US11411265
申请日：2006-04-26
申请人： Alan G. Wood , Kyle K. Kirby , Warren M. Farnworth , Salman Akram
发明人： Alan G. Wood , Kyle K. Kirby , Warren M. Farnworth , Salman Akram
IPC分类号： H01L23/02
CPC分类号： H01L27/14618 , B33Y80/00 , H01L27/14625 , H01L2224/48091 , H01L2924/00014
摘要： A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used.
摘要翻译：诸如图像传感器封装的半导体封装。框架结构包括每个具有穿过其中的孔的框架阵列，图像传感器与盖玻片，过滤器，透镜或其它部件组合的模具可以精确地相互对准地安装在该框架中。单片图像传感器骰子和其他组件可以被拾取并放置在框架结构的每个帧中。或者，框架结构可以被配置为与承载多个图像传感器骰子的晶片对准并且连接到其上，其中沿着框架的周边的任选的向下突出的裙边可以被接收到沿着晶片上的模具位置之间沿着街道切割的切口，然后安装其他包装组件。在任一情况下，将帧结构与单独的图像传感器芯片或连接的晶片组合成单独的图像传感器封装。可以使用各种外部连接方法。

136. 发明授权

US06998344B2 Method for fabricating semiconductor components by forming conductive members using solder 失效
标题翻译：通过使用焊料形成导电部件来制造半导体部件的方法
公开(公告)号：US06998344B2
公开(公告)日：2006-02-14
申请号：US10815083
申请日：2004-03-31
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L21/44
CPC分类号： H01L24/81 , H01L21/486 , H01L21/76898 , H01L23/13 , H01L23/49827 , H01L23/5389 , H01L24/16 , H01L24/75 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2224/48227 , H01L2224/75 , H01L2224/81801 , H01L2224/82039 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H05K1/0306 , H05K1/112 , H05K3/0029 , H05K3/0032 , H05K2201/09472 , H05K2201/0959 , H05K2201/09827 , H05K2201/09845 , H05K2201/10674 , H05K2201/10734 , H01L2924/00 , H01L2224/05599
摘要： An interconnect for semiconductor components such as dice, wafers and chip scale packages is provided. The interconnect includes a substrate, and patterns of contacts formed on a face side of the substrate adapted to electrically engage external contacts (e.g., bond pads, solder bumps) on the components. The interconnect also includes insulated conductive members through the substrate, which provide direct electrical paths from the interconnect contacts to a backside of the substrate. The conductive members can be formed by laser machining openings in the substrate, and then filling the openings with a conductive material (e.g., metal, conductive polymer). The conductive members can also include pads with contact balls, configured for electrical interface with a test apparatus, such as test carrier or wafer handler. The interconnect can be used to construct test systems for testing semiconductor components, or to construct chip scale packages and multi chip modules.
摘要翻译：提供了诸如骰子，晶片和芯片级封装的半导体元件的互连。互连包括衬底和形成在衬底的面侧上的触点图案，其适于电耦合组件上的外部触点（例如，接合焊盘，焊料凸块）。互连还包括通过衬底的绝缘导电构件，其提供从互连触点到衬底背面的直接电路径。导电构件可以通过在衬底中激光加工开口形成，然后用导电材料（例如金属，导电聚合物）填充开口。导电构件还可以包括具有接触球的焊盘，其被配置为与诸如测试载体或晶片处理器的测试装置电接口。互连可用于构建用于测试半导体元件的测试系统，或构建芯片级封装和多芯片模块。

137. 发明授权

US06953995B2 Hermetic chip in wafer form 失效
标题翻译：晶圆形密封芯片
公开(公告)号：US06953995B2
公开(公告)日：2005-10-11
申请号：US10624766
申请日：2003-07-22
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： H01L21/56 , H01L23/29 , H01L23/31 , H01L23/485 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L21/56 , H01L23/291 , H01L23/3107 , H01L24/03 , H01L24/48 , H01L2224/04042 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48464 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01031 , H01L2924/01032 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/10253 , Y10S438/958 , Y10S438/959 , H01L2224/45099 , H01L2924/00 , H01L2224/85399
摘要： A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process for the fully hermetic sealing of both sides and the edges of the semiconductor chip without the use of a separate package.
摘要翻译：一种完全密封的半导体芯片及其制造方法。本发明的半导体芯片通过使用适用于其上的合适的涂层（例如玻璃）在其两侧及其边缘上完全气密密封，以防止半导体芯片的环境攻击。本发明的完全密封的半导体芯片不需要使用用于芯片的气密密封的单独封装，从而减小这种芯片的尺寸。本发明的半导体芯片的制造方法提供了一种使半导体芯片的两面和边缘完全密封的简单方法，而不需要使用单独的封装。

138. 发明授权

US06952054B2 Semiconductor package having interconnect with conductive members 失效
标题翻译：具有与导电构件互连的半导体封装
公开(公告)号：US06952054B2
公开(公告)日：2005-10-04
申请号：US10820674
申请日：2004-04-08
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L21/48 , H01L21/60 , H01L21/768 , H01L23/13 , H01L23/498 , H01L23/538 , H01L25/10 , H05K1/03 , H05K1/11 , H05K3/00 , H01L23/48
CPC分类号： H01L24/81 , H01L21/486 , H01L21/76898 , H01L23/13 , H01L23/49827 , H01L23/5389 , H01L24/16 , H01L24/75 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2224/48227 , H01L2224/75 , H01L2224/81801 , H01L2224/82039 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H05K1/0306 , H05K1/112 , H05K3/0029 , H05K3/0032 , H05K2201/09472 , H05K2201/0959 , H05K2201/09827 , H05K2201/09845 , H05K2201/10674 , H05K2201/10734 , H01L2924/00 , H01L2224/05599
摘要： An interconnect for semiconductor components such as dice, wafers and chip scale packages is provided. The interconnect includes a substrate, and patterns of contacts formed on a face side of the substrate adapted to electrically engage external contacts (e.g., bond pads, solder bumps) on the components. The interconnect also includes insulated conductive members through the substrate, which provide direct electrical paths from the interconnect contacts to a backside of the substrate. The conductive members can be formed by laser machining openings in the substrate, and then filling the openings with a conductive material (e.g., metal, conductive polymer). The conductive members can also include pads with contact balls, configured for electrical interface with a test apparatus, such as test carrier or wafer handler. The interconnect can be used to construct test systems for testing semiconductor components, or to construct chip scale packages and multi chip modules.
摘要翻译：提供了诸如骰子，晶片和芯片级封装的半导体元件的互连。互连包括衬底和形成在衬底的面侧上的触点图案，其适于电耦合组件上的外部触点（例如，接合焊盘，焊料凸块）。互连还包括通过衬底的绝缘导电构件，其提供从互连触点到衬底背面的直接电路径。导电构件可以通过在衬底中激光加工开口形成，然后用导电材料（例如金属，导电聚合物）填充开口。导电构件还可以包括具有接触球的焊盘，其被配置为与诸如测试载体或晶片处理器的测试装置电接口。互连可用于构建用于测试半导体元件的测试系统，或构建芯片级封装和多芯片模块。

139. 发明授权

US06909055B2 Electrical device allowing for increased device densities 失效
标题翻译：电气设备允许增加设备密度
公开(公告)号：US06909055B2
公开(公告)日：2005-06-21
申请号：US10301990
申请日：2002-11-22
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
IPC分类号： H01L23/495 , H05K1/02 , H05K1/09 , H05K3/32 , H05K1/11
CPC分类号： H05K3/4007 , H01L23/4951 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H05K1/0271 , H05K1/095 , H05K3/321 , H05K3/325 , H05K3/326 , H05K2201/0133 , H05K2201/0314 , H05K2201/0367 , H05K2201/09909 , H05K2201/10454 , H05K2201/10696 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate.
摘要翻译：一种装置，包括电路，具有连接到所述电路并具有第二端的第一端的引线和连接到所述引线的第二端的可变形结构。本发明可以实现在电路板上，使得电路板包括基板和连接到所述基板的可变形结构。

140. 发明授权

US06634100B2 Interposer and methods for fabricating same 有权
标题翻译：中介层的制造方法
公开(公告)号：US06634100B2
公开(公告)日：2003-10-21
申请号：US09843119
申请日：2001-04-26
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01R4316
CPC分类号： H05K7/1061 , B33Y10/00 , B33Y30/00 , B33Y80/00 , G01R1/0408 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/07378 , G01R3/00 , H01L23/32 , H01L23/49827 , H01L2224/16111 , H01L2224/16237 , H01L2224/8114 , H01L2224/81385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01049 , H01L2924/01082 , H01L2924/12042 , H01L2924/12044 , H01L2924/15787 , H01L2924/351 , H05K1/112 , H05K1/141 , H05K3/3436 , H05K2201/049 , H05K2201/09472 , H05K2201/10378 , H05K2201/10734 , H05K2201/2018 , H05K2203/167 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： Methods for fabricating an interposer, wherein the fence include the use of stereolithographic and molding processes. When stereolithography is used to fabricate the fence, a machine vision system that includes at least one camera operably associated with a computer may be used to control a stereolithography apparatus and facilitates recognition of the position and orientation of interposer substrates on and around which material is to be applied in one or more layers to form the fence. As a result, the interposer substrates need not be precisely mechanically aligned.
摘要翻译：用于制造插入件的方法，其中所述栅栏包括使用立体光刻和成型工艺。当使用立体光刻制造栅栏时，可以使用包括与计算机可操作地相关联的至少一个照相机的机器视觉系统来控制立体光刻设备并且有助于识别材料在其上和周围的插入物基板的位置和取向应用于一层或多层以形成栅栏。结果，内插器基板不需要精确地机械对准。

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