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131. 发明授权

US5498562A Semiconductor processing methods of forming stacked capacitors 失效
公开(公告)号：US5498562A
公开(公告)日：1996-03-12
申请号：US237371
申请日：1994-04-29
申请人： Charles H. Dennison , Michael A. Walker
发明人： Charles H. Dennison , Michael A. Walker
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： In one aspect of the invention, an insulative nitride oxidation barrier layer is provided over a cell polysilicon layer to a thickness of at least about 150 Angstroms. An insulating layer is provided above the nitride oxidation barrier layer, and an contact/container is etched therethrough and through dielectric and cell polysilicon layers. Such exposes edges of the cell polysilicon within the contact/container. The wafer is then exposed to an oxidizing ambient to oxidize the cell polysilicon exposed edges, with the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer. In another aspect, a multi-container stacked capacitor construction has its containers defined or otherwise electrically isolated in a single CMP step. In another aspect, a combination etch stop/oxidation barrier layer or region is provided to enable exposure of a precise quantity of the outside walls of a stacked capacitor container.

132. 发明授权

US5397908A Arrays of memory integrated circuitry 失效
标题翻译：存储器集成电路阵列
公开(公告)号：US5397908A
公开(公告)日：1995-03-14
申请号：US164896
申请日：1993-12-09
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L21/76 , H01L21/108 , H01L21/762 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/78 , H01L29/68 , H01L27/12
CPC分类号： H01L27/10852 , H01L21/76224 , H01L21/823481 , Y10S148/05
摘要： A semiconductor processing device isolation method includes: a) providing non-LOCOS insulating device isolation blocks by trench and refill technique on a substrate to define recessed moat volume therebetween; b) providing gate dielectric within the moat volume; c) providing a layer of electrically conductive material over the substrate and gate dielectric to a thickness sufficient to completely fill the moat volume between adjacent isolation blocks; d) chemical-mechanical polishing the layer of electrically conductive material to provide a planarized upper electrically conductive material surface; e) photopatterning and etching the layer of electrically conductive material to provide an electrically conductive runner which overlies a plurality of the isolation blocks and to selectively remove the electrically conductive material from within selected regions of moat volume to define field effect transistor gates within the moat volume; and f) providing conductivity enhancing impurity through the selected regions of moat volume into the substrate to define source/drain regions adjacent the field effect transistor gates. The invention also includes an array of memory integrated circuitry.
摘要翻译：半导体处理器件隔离方法包括：a）通过沟槽和再填充技术在衬底上提供非LOCOS绝缘器件隔离块，以在其间限定凹陷的沟槽体积; b）在护城河容积内提供栅极电介质; c）在衬底和栅极电介质上提供一层导电材料，其厚度足以完全填充相邻隔离块之间的护城河体积; d）化学机械抛光导电材料层以提供平坦化的上导电材料表面; e）对导电材料层进行光图案化和蚀刻，以提供覆盖在多个隔离块上的导电浇道，并且选择性地从导流槽体积的选定区域内去除导电材料，以在护城河体积内限定场效应晶体管栅极 ; 以及f）通过所选择的沟槽体积的区域提供导电性增强杂质到衬底中以限定与场效应晶体管栅极相邻的源极/漏极区域。本发明还包括一组存储器集成电路。

133. 发明授权

US5371701A Stacked delta cell capacitor 失效
标题翻译：堆叠式三角形电容器
公开(公告)号：US5371701A
公开(公告)日：1994-12-06
申请号：US223477
申请日：1994-04-05
申请人： Ruojia Lee , Charles H. Dennison , Yauh-Ching Liu , Pierre Fazan , Steven D. Cummings
发明人： Ruojia Lee , Charles H. Dennison , Yauh-Ching Liu , Pierre Fazan , Steven D. Cummings
IPC分类号： H01L27/108 , H01L29/68
CPC分类号： H01L27/10817
摘要： A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.
摘要翻译：使用改进的堆叠电容器存储单元制造工艺的堆叠三角形电池（SDC）电容器。 SDC由具有倒三角形横截面的多晶硅结构构成，位于掩埋接触处，并延伸到由多晶硅覆盖的相邻存储节点之间，介电夹在其间。多晶硅结构的添加增加了存储能力120％，而不会扩大为正常层叠电容器单元限定的表面积。

134. 发明授权

US5362666A Method of producing a self-aligned contact penetrating cell plate 失效
标题翻译：制造自对准接触穿透细胞板的方法
公开(公告)号：US5362666A
公开(公告)日：1994-11-08
申请号：US213381
申请日：1994-03-15
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L27/108 , H01L21/70
CPC分类号： H01L27/10817 , Y10S438/97
摘要： After formation of the storage poly in a stacked capacitor DRAM, the oxide 1 layer is partially etched to leave a thick oxide deposition in the area of the future bit line contact, upon which the cell poly is deposited, followed by oxide 2 and then a poly or nitride layer. A mask and etch process forms the bit line contact region through the cell poly, then a thin oxide is deposited and etched along with the oxide 1 to form cell poly spacers that don't close off the active area. The poly or nitride on top of the oxide 2 forms a hard mask that allows the spacers to travel down the side walls of the contact region creating a contact region that is wider at the top than bottom, facilitating metalization.
摘要翻译：在叠层电容器DRAM中形成储存多晶硅之后，氧化层1层被部分蚀刻，以便在将来的位线接触区域中留下厚的氧化物沉积，沉积电池多晶，然后是氧化物2，然后是聚或氮化物层。掩模和蚀刻工艺通过电池多孔形成位线接触区域，然后与氧化物1一起沉积和蚀刻薄氧化物，以形成不关闭有源区域的电池聚合间隔物。氧化物2顶部上的聚氮化物或氮化物形成硬掩模，其允许间隔物沿接触区域的侧壁向下移动，形成在顶部比底部更宽的接触区域，有利于金属化。

135. 发明授权

US5348899A Method of fabricating a bottom and top gated thin film transistor 失效
标题翻译：制造底部和顶部门控薄膜晶体管的方法
公开(公告)号：US5348899A
公开(公告)日：1994-09-20
申请号：US75035
申请日：1993-06-10
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L21/265
CPC分类号： H01L29/6675 , H01L27/11 , H01L27/1108 , H01L29/66757 , H01L29/78618 , Y10S148/131 , Y10S148/15
摘要： An electric interconnection method includes: a) providing two conductive layers separated by including material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.
摘要翻译：电互连方法包括：a）提供通过在半导体晶片上包括材料而分离的两个导电层; b）蚀刻导电层和绝缘材料以限定和向外暴露每个导电层的侧壁; c）在蚀刻的导电层及其各自的侧壁上沉积导电材料; 以及d）各向异性蚀刻所述导电材料以限定将所述两个导电层电连接的导电侧壁连接件。这样可用于制造薄膜晶体管和其他电路。

136. 发明授权

US5346587A Planarization of a gate electrode for improved gate patterning over non-planar active area isolation 失效
标题翻译：用于在非平面有源区隔离上改善栅极图案化的栅电极的平面化
公开(公告)号：US5346587A
公开(公告)日：1994-09-13
申请号：US105276
申请日：1993-08-12
申请人： Trung T. Doan , Charles H. Dennison
发明人： Trung T. Doan , Charles H. Dennison
IPC分类号： H01L21/28 , H01L21/768 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/00
CPC分类号： H01L21/28123 , H01L21/7684
摘要： The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.
摘要翻译：本发明是一种在非平面起始衬底上提供平面化晶体管栅极的方法，通过沉积覆盖相邻场氧化物隔离区域的平坦化导电多晶硅材料层，使得导电多晶硅材料的高度延伸到场氧化物隔离区; 将导电硅化物材料层沉积在导电多晶硅材料上方并共同延伸; 然后对平坦化的导电多晶硅材料和导电硅化物材料进行构图，从而形成平坦化的晶体管栅极。

137. 发明授权

US5262343A DRAM stacked capacitor fabrication process 失效
标题翻译： DRAM堆叠电容器制造工艺
公开(公告)号：US5262343A
公开(公告)日：1993-11-16
申请号：US852822
申请日：1992-03-06
申请人： Howard E. Rhodes , Pierre Fazan , Hiang C. Chan , Charles H. Dennison , Yauh-Ching Liu
发明人： Howard E. Rhodes , Pierre Fazan , Hiang C. Chan , Charles H. Dennison , Yauh-Ching Liu
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/70
CPC分类号： H01L27/10852 , H01L28/40
摘要： This invention relates to semiconductor circuit memory storage devices and more particularly to a process to develop three-dimensional stacked capacitor cells using a high dielectric constant material as a storage cell dielectric and a combination of conductively doped polysilicon and metal silicide as the capacitor plates of a storage cell for use in high-density dynamic random access memory (DRAM) arrays. The present invention teaches how to fabricate three-dimensional stacked capacitors by modifying an existing stacked capacitor fabrication process to construct the three-dimensional stacked capacitor cell incorporating a high dielectric constant material as the cell dielectric that will allow denser storage cell fabrication with minimal increases of overall memory array dimensions. A capacitance gain of 3 to 10.times. or more over that of a conventional 3-dimensional storage cell is gained by using a high dielectric constant material as the storage cell dielectric.
摘要翻译：本发明涉及半导体电路存储器存储器件，更具体地说，涉及使用高介电常数材料作为存储单元电介质和导电掺杂多晶硅和金属硅化物的组合来开发三维叠层电容器单元的方法，作为电容器板用于高密度动态随机存取存储器（DRAM）阵列的存储单元。本发明教导了如何通过修改现有的层叠电容器制造工艺来制造三维层叠电容器，以构建结合有高介电常数材料的三维叠层电容器单元作为电池电介质，其将使得更密集的存储单元制造以最小的增加整体内存阵列尺寸。通过使用高介电常数材料作为存储单元电介质，获得比常规3维存储单元的电容增益高3至10倍或更多的电容增益。

138. 发明授权

US5244837A Semiconductor electrical interconnection methods 失效
标题翻译：半导体电气互连方式
公开(公告)号：US5244837A
公开(公告)日：1993-09-14
申请号：US33830
申请日：1993-03-19
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L21/768
CPC分类号： H01L21/76802 , H01L21/76801 , H01L21/76807 , H01L21/76877
摘要： A semiconductor metallization processing method for multi-level electrical interconnection includes: a) providing a base insulating layer atop a semiconductor wafer; b) etching a groove pathway into the base layer; c) providing a first contact through the base layer to the area to which electrical connection is to be made; d) the groove pathway being etched and the first contact being provided in a combined manner which has the groove pathway and the first contact communicating with one another; e) providing metal within the first contact and within the groove pathway, the metal provided within the first contact and groove pathway in combination defining a first metal layer, the first metal layer having an overall thickness which is sufficient to fill the first contact and groove pathway; f) planarizing the first metal layer back to the uppermost region to form a conductive metal runner within the groove pathway; g) providing an overlying layer of insulating material which is different in composition from the base layer uppermost region; h) etching through the overlying layer selectively relative to the uppermost region to provide a second contact to the conductive metal runner which overlaps the conductive metal runner and uppermost region of insulating material of the base layer, the conductive metal runner being void of surround where the second contact overlaps the conductive metal runner; and i) depositing and patterning a second metal layer atop the etched overlying layer of insulating material.
摘要翻译：一种用于多电平电互连的半导体金属化处理方法包括：a）在半导体晶片的顶部设置基极绝缘层; b）蚀刻沟槽通道进入基层; c）通过基底层提供到要进行电连接的区域的第一接触; d）所述凹槽通路被蚀刻，并且所述第一触点以组合的方式设置，所述组合方式具有所述凹槽通路并且所述第一触头彼此连通; e）在所述第一接触件内部和在所述沟槽通道内提供金属，所述金属设置在所述第一接触槽和沟槽通道内，其组合限定第一金属层，所述第一金属层具有足以填充所述第一接触和凹槽的总厚度途径 f）将第一金属层平面化回最上部区域，以在凹槽通路内形成导电金属流道; g）提供与基底层最上部区域的组成不同的绝缘材料的上覆层; h）相对于最上部区域选择性地蚀刻穿过覆盖层，以提供与导电金属流道和基层绝缘材料的最上部区域重叠的导电金属流道的第二接触，导电金属流道没有环绕，其中第二触点与导电金属流道重叠; 以及i）在蚀刻的绝缘材料的上覆层上方沉积和图案化第二金属层。

139. 发明授权

US5198384A Process for manufacturing a ferroelectric dynamic/non-volatile memory array using a disposable layer above storage-node junction 失效
标题翻译：使用存储节点结上方的一次性层制造铁电动态/非易失性存储器阵列的方法
公开(公告)号：US5198384A
公开(公告)日：1993-03-30
申请号：US700747
申请日：1991-05-15
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/10852 , H01L28/55
摘要： A process for manufacturing a ferroelectric memory array of stacked-cell design that can be operated in both dynamic and nonvolatile modes. The process deviates from conventional stacked cell array processing at the storage node plate formation stage. A storage node polysilicon layer is conformally deposited, while being in-situ conductively doped, to a depth greater than that necessary to completely fill inter-wordline gaps (if not already planarized) and inter-bitline gaps (in the case of a buried digit line process flow). The storage-node poly layer is then planarized to a level at which poly still covers the entire array. Next, a barrier layer of a refractory metal (e.g., platinum) or of a refractory metal silicide is created on top of the planarized storage-node poly layer. A disposable polyimide layer, which is deposited on top of the barrier layer, is patterned during the same step in which the storage node contact layer and barrier layer are patterned. A silicon dioxide layer is subsequently created via low-temperature chemical vapor deposition. After the this silicon dioxide layer is planarized, thus exposing the polyimide layer remnants, the latter are removed. Next, a PZT dielectric layer is deposited via either the well-known solution-gelatin technique or sputtering. Finally, a refractory metal or refractory metal silicide cell plate layer is deposited. The memory array is completed using standard processing from this point.
摘要翻译：用于制造可以以动态和非易失性模式操作的堆叠单元设计的铁电存储器阵列的方法。该过程偏离存储节点板形成阶段的常规堆叠单元阵列处理。存储节点多晶硅层在原位导电掺杂的同时沉积到深度大于完全填充字间间距（如果尚未平面化）和位线间间隙所需的深度（在掩埋位数的情况下线工艺流程）。然后将存储节点多层平面化到聚合物仍覆盖整个阵列的水平。接下来，在平坦化的存储节点多层的顶部上形成难熔金属（例如铂）或难熔金属硅化物的阻挡层。沉积在阻挡层顶部上的一次性聚酰亚胺层在其中对存储节点接触层和阻挡层进行图案化的相同步骤中被图案化。随后通过低温化学气相沉积形成二氧化硅层。在将该二氧化硅层平坦化之后，由此露出聚酰亚胺层残留物，后者被去除。接下来，通过公知的溶液 - 明胶技术或溅射沉积PZT电介质层。最后，沉积难熔金属或难熔金属硅化物电池板层。从这一点开始，使用标准处理完成存储器阵列。

140. 发明授权

US5084406A Method for forming low resistance DRAM digit-line 失效
标题翻译：低电阻DRAM数位线形成方法
公开(公告)号：US5084406A
公开(公告)日：1992-01-28
申请号：US724026
申请日：1991-07-01
申请人： Howard E. Rhodes , Pierre C. Fazan , Hiang C. Chan , Charles H. Dennison , Yauh-Ching Liu
发明人： Howard E. Rhodes , Pierre C. Fazan , Hiang C. Chan , Charles H. Dennison , Yauh-Ching Liu
IPC分类号： G11C11/401 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/10 , H01L27/108
CPC分类号： H01L23/53271 , H01L21/768 , H01L23/5283 , H01L2924/0002
摘要： A DRAM fabrication process is disclosed for constructing a reduced resistance digit-line. The digit-line is so constructed as to maintain low resistance as it crosses the gaps between word-lines. By bridging gaps having a dimension less than or falling below a calculated critical gap spacing, and following the contours of gaps having a dimension greater or falling above that critical gap dimension, the digit-line resistance can be minimized.
摘要翻译：公开了用于构造减小电阻数字线的DRAM制造工艺。数字线被构造成当它跨越字线之间的间隙时保持低电阻。通过桥接具有小于或低于计算的临界间隙的尺寸的间隙，并且跟随具有大于或低于该临界间隙尺寸的尺寸的间隙的轮廓，可以使数字线电阻最小化。

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