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131. 发明授权

US08497528B2 Method for fabricating a strained structure 有权
标题翻译：制造应变结构的方法
公开(公告)号：US08497528B2
公开(公告)日：2013-07-30
申请号：US12775006
申请日：2010-05-06
申请人： Tsung-Lin Lee , Chih-Hao Chang , Chih-Hsin Ko , Feng Yuan , Jeff J. Xu
发明人： Tsung-Lin Lee , Chih-Hao Chang , Chih-Hsin Ko , Feng Yuan , Jeff J. Xu
IPC分类号： H01L29/66
CPC分类号： H01L29/7848 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L21/30604 , H01L21/31 , H01L21/31116 , H01L21/76 , H01L29/0653 , H01L29/0847 , H01L29/0856 , H01L29/0873 , H01L29/1608 , H01L29/165 , H01L29/6653 , H01L29/66553 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.
摘要翻译：一种用于衬底上的场效应晶体管的结构，其包括栅极堆叠，隔离结构以及位于栅叠层和隔离结构之间的衬底顶表面下方的源极/漏极（S / D）凹槽。该凹腔具有下部和上部。下部具有第一应变层和第一介电膜。第一应变层设置在隔离结构和第一介电膜之间。第一电介质膜的厚度小于第一应变层的厚度。上部具有覆盖在第一应变层和第一介电膜上的第二应变层。

132. 发明申请

US20110223727A1 CMOS Devices with Schottky Source and Drain Regions 有权
标题翻译：具有肖特基源和漏极区域的CMOS器件
公开(公告)号：US20110223727A1
公开(公告)日：2011-09-15
申请号：US13113530
申请日：2011-05-23
申请人： Chih-Hsin Ko , Hung-Wei Chen , Chung-Hu Ke , Wen-Chin Lee
发明人： Chih-Hsin Ko , Hung-Wei Chen , Chung-Hu Ke , Wen-Chin Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L29/1054 , H01L29/165 , H01L29/47 , H01L29/665 , H01L29/6653 , H01L29/66568 , H01L29/6659 , H01L29/66643 , H01L29/7843
摘要： A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.
摘要翻译：半导体结构包括半导体衬底和在半导体衬底的表面处的NMOS器件，其中NMOS器件包括肖特基源极/漏极延伸区域。半导体结构还包括在半导体衬底的表面处的PMOS器件，其中PMOS器件包括仅包含非金属材料的源极/漏极延伸区域。可以为PMOS器件和NMOS器件形成肖特基源极/漏极延伸区域，其中通过在具有低价带的半导体层上形成PMOS器件来减小PMOS器件的肖特基势垒高度。

133. 发明授权

US07985652B2 Metal stress memorization technology 有权
标题翻译：金属应力记忆技术
公开(公告)号：US07985652B2
公开(公告)日：2011-07-26
申请号：US11855701
申请日：2007-09-14
申请人： Chung-Hu Ke , Ta-Ming Kuan , Chih-Hsin Ko , Wen-Chin Lee
发明人： Chung-Hu Ke , Ta-Ming Kuan , Chih-Hsin Ko , Wen-Chin Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L29/665 , H01L29/7847
摘要： A semiconductor device and method for manufacturing a tensile strained NMOS and a compressive strained PMOS transistor pair, wherein a stressor material is sacrificial is disclosed. The method provides for a substrate, which includes a source/drain for an NMOS transistor, and a PMOS transistor. A first barrier layer is formed on the substrate and a first stressor material is formed on the first barrier layer. The first barrier layer is selectively removed from the PMOS transistor. The substrate is flash annealed and the remaining first stressor material and barrier layer is removed from the substrate.
摘要翻译：公开了用于制造拉伸应变NMOS和压缩应变PMOS晶体管对的半导体器件和方法，其中应力源材料是牺牲的。该方法提供了一种衬底，其包括用于NMOS晶体管的源极/漏极和PMOS晶体管。在基板上形成第一阻挡层，在第一阻挡层上形成第一应力源材料。从PMOS晶体管选择性地去除第一势垒层。衬底被闪光退火，剩余的第一应力材料和阻挡层从衬底上去除。

134. 发明授权

US07867860B2 Strained channel transistor formation 有权
标题翻译：应变通道晶体管形成
公开(公告)号：US07867860B2
公开(公告)日：2011-01-11
申请号：US10897563
申请日：2004-07-23
申请人： Yi-Chun Huang , Yen-Ping Wang , Chih-Hsin Ko
发明人： Yi-Chun Huang , Yen-Ping Wang , Chih-Hsin Ko
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L29/41783 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7842 , H01L29/7848 , Y10S438/938
摘要： A strained channel transistor is provided. The strained channel transistor comprises a substrate formed of a first material. A source region comprised of a second material is formed in a first recess in the substrate, and a drain region comprised of the second material is formed in a second recess in the substrate. A strained channel region formed of the first material is intermediate the source and drain region. A gate stack formed over the channel region includes a gate electrode overlying a gate dielectric. A gate spacer formed along a sidewall of the gate electrode overlies a portion of at least one of said source region and said drain region. A cap layer may be formed over the second material, and the source and drain regions may be silicided.
摘要翻译：提供了一个应变通道晶体管。应变通道晶体管包括由第一材料形成的衬底。由第二材料构成的源极区域形成在基板的第一凹部中，并且由第二材料构成的漏极区域形成在基板的第二凹部中。由第一材料形成的应变通道区域在源区和漏区之间。形成在通道区域上方的栅极叠层包括覆盖栅极电介质的栅电极。沿着栅电极的侧壁形成的栅极间隔物覆盖至少一个所述源极区域和漏极区域的一部分。可以在第二材料上形成覆盖层，并且源极和漏极区域可以被硅化。

135. 发明授权

US07803718B2 BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture 有权
标题翻译：通过机械单轴应变的BiCMOS性能提高和制造方法
公开(公告)号：US07803718B2
公开(公告)日：2010-09-28
申请号：US12260674
申请日：2008-10-29
申请人： Chih-Hsin Ko , Tzu-Juei Wang , Hung-Wei Chen , Chung-Hu Ke , Wen-Chin Lee
发明人： Chih-Hsin Ko , Tzu-Juei Wang , Hung-Wei Chen , Chung-Hu Ke , Wen-Chin Lee
IPC分类号： H01L23/31
CPC分类号： H01L21/8249 , H01L21/823807 , H01L27/0623 , H01L29/7843
摘要： A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.
摘要翻译：提供了通过机械单轴应变增强性能的BiCMOS器件。本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。

136. 发明授权

US07745904B2 Shallow trench isolation structure for semiconductor device 有权
标题翻译：用于半导体器件的浅沟槽隔离结构
公开(公告)号：US07745904B2
公开(公告)日：2010-06-29
申请号：US11809519
申请日：2007-05-31
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L29/00
CPC分类号： H01L29/0847 , H01L21/76232 , H01L21/823481 , H01L29/66636 , H01L29/7834
摘要： A semiconductor device provides a transistor adjacent an isolation trench. The device may be formed by producing isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the trenches causing the edges to become rounded and overhang the trench. The filler material may be a dielectric. The transistors which are then formed in close proximity to the trenches may include source/drain regions formed in the rounded portion of the semiconductor substrate that overhangs the trench.
摘要翻译：半导体器件提供与隔离沟槽相邻的晶体管。该器件可以通过在半导体衬底中产生隔离沟槽，用填充材料填充沟槽，在沟槽的顶部边缘附近产生空隙，并通过气态环境进行退火以使沟槽的边缘回流，从而使边缘变圆; 突出沟槽。填充材料可以是电介质。然后形成在靠近沟槽的晶体管可以包括形成在半导体衬底的圆形部分中的突出于沟槽的源极/漏极区域。

137. 发明授权

US07465620B2 Transistor mobility improvement by adjusting stress in shallow trench isolation 有权
标题翻译：通过调整浅沟槽隔离中的应力来提高晶体管的迁移率
公开(公告)号：US07465620B2
公开(公告)日：2008-12-16
申请号：US11702399
申请日：2007-02-05
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/44
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823878 , H01L29/665 , H01L29/78
摘要： A method of improving the carrier mobility of a transistor is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide layer is formed on the source/drain region. After the step of forming the silicide layer, a recess is formed by etching the dielectric so that the surface of the dielectric is substantially lower than the surface of the substrate. Recessing the STI causes the removal of the compressive stress applied to the channel region by the STI material. A contact etch stop layer (CESL) is formed over the gate electrode, spacers, source/drain region and the dielectric. The CESL applies a desired stress to the channel region. Trench liners may optionally be formed to provide a stress to the channel region. A trench spacer may optionally be formed in the STI recess.
摘要翻译：提出了一种提高晶体管载流子迁移率的方法。在衬底中形成沟槽。沟槽填充有电介质。在沟槽附近形成CMOS晶体管。在源极/漏极区域上形成硅化物层。在形成硅化物层的步骤之后，通过蚀刻电介质形成凹陷，使得电介质的表面基本上低于衬底的表面。嵌入STI导致STI材料去除施加到沟道区域的压应力。在栅电极，间隔物，源/漏区和电介质上形成接触蚀刻停止层（CESL）。 CESL对通道区域施加所需的应力。可以可选地形成沟槽衬垫以向通道区域提供应力。可以可选地在STI凹部中形成沟槽间隔物。

138. 发明申请

US20080185659A1 Semiconductor device and a method of fabricating the device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080185659A1
公开(公告)日：2008-08-07
申请号：US11703365
申请日：2007-02-07
申请人： Chung-Hu Ke , Chih-Hsin Ko , Wen-Chin Lee
发明人： Chung-Hu Ke , Chih-Hsin Ko , Wen-Chin Lee
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/66606 , H01L29/78 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress film over the poly region. In a PMOS device, the ultra-stressor layer includes a compressive stress film over the source and drain regions and a tensile stress film over the poly region. In a preferred embodiment, the semiconductor device includes a PMOS transistor and an NMOS transistor forming a CMOS device and covered with an ultra stressor layer.
摘要翻译：具有被超应力层覆盖的至少一个晶体管的半导体器件及其制造方法。在NMOS器件中，超应力层包括源极和漏极区域上的拉伸应力膜，以及多个区域上的压应力膜。在PMOS器件中，超应力层包括源极和漏极区域上的压缩应力膜和在多个区域上的拉伸应力膜。在优选实施例中，半导体器件包括PMOS晶体管和形成CMOS器件并被超压应力层覆盖的NMOS晶体管。

139. 发明授权

US07394136B2 High performance semiconductor devices fabricated with strain-induced processes and methods for making same 有权
标题翻译：用应变诱导工艺制造的高性能半导体器件及其制造方法
公开(公告)号：US07394136B2
公开(公告)日：2008-07-01
申请号：US11194084
申请日：2005-07-29
申请人： Chung-Hu Ke , Wen-Chin Lee , Yee-Chia Yeo , Chih-Hsin Ko , Chenming Hu
发明人： Chung-Hu Ke , Wen-Chin Lee , Yee-Chia Yeo , Chih-Hsin Ko , Chenming Hu
IPC分类号： H01L21/00
CPC分类号： H01L29/7846 , H01L21/823807 , H01L21/823878 , H01L29/1033 , H01L29/78 , H01L29/7842
摘要： A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.
摘要翻译：公开了一种改进的驱动电流的高性能半导体器件及其制造方法。半导体器件具有构建在有源区上的源极和漏极区域，器件的长度与其宽度不同。在有源区周围制造一个或多个隔离区域，然后用退火处理后其体积收缩率超过0.5％的预定隔离材料填充隔离区域。在有源区上形成栅电极，并且在栅电极旁边形成一个或多个电介质间隔物。然后，接触蚀刻停止层放置在器件上，其中隔离区，间隔物和接触蚀刻层有助于调制施加在有源区上的净应变，以便改善驱动电流。

140. 发明申请

US20070161206A1 Isolation structure for strained channel transistors 审中-公开
标题翻译：应变通道晶体管的隔离结构
公开(公告)号：US20070161206A1
公开(公告)日：2007-07-12
申请号：US11586936
申请日：2006-10-26
申请人： Chih-Hsin Ko , Yee-Chia Yeo , Wen-Chin Lee , Chung-Hu Ge
发明人： Chih-Hsin Ko , Yee-Chia Yeo , Wen-Chin Lee , Chung-Hu Ge
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L29/1054 , H01L29/7846 , H01L29/7848
摘要： A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.
摘要翻译：公开了用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。

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