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121. 发明授权

US09257642B1 Protective sidewall techniques for RRAM 有权
标题翻译： RRAM的保护侧壁技术
公开(公告)号：US09257642B1
公开(公告)日：2016-02-09
申请号：US14332577
申请日：2014-07-16
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yao-Wen Chang , Jian-Shiou Huang , Hsing-Lien Lin , Cheng-Yuan Tsai , Chia-Shiung Tsai
IPC分类号： H01L27/24 , H01L27/112 , H01L29/417 , H01L29/45 , H01L29/86 , H01L45/00
CPC分类号： H01L45/1253 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： Some embodiments relate to a resistive random access memory (RRAM). The RRAM includes a RRAM bottom metal electrode, a variable resistance dielectric layer arranged over the RRAM bottom metal electrode, and a RRAM top metal electrode arranged over the variable resistance dielectric layer. A capping layer is arranged over the RRAM top metal electrode. A lower surface of the capping layer and an upper surface of the RRAM top metal electrode meet at an interface. Protective sidewalls are adjacent to outer sidewalls of the RRAM top metal electrode. The protective sidewalls have upper surfaces at least substantially aligned to the interface at which the upper surface of the RRAM top metal electrode meets the lower surface of the capping layer.
摘要翻译：一些实施例涉及电阻随机存取存储器（RRAM）。 RRAM包括RRAM底部金属电极，布置在RRAM底部金属电极上的可变电阻介电层和布置在可变电阻介电层上的RRAM顶部金属电极。在RRAM顶部金属电极上设置覆盖层。覆盖层的下表面和RRAM顶部金属电极的上表面在界面处相遇。保护侧壁与RRAM顶部金属电极的外侧壁相邻。保护侧壁的上表面至少基本上与RRAM顶部金属电极的上表面与覆盖层的下表面相接触的界面对齐。

122. 发明授权

US09190894B2 Bidirectional two-base bipolar junction transistor operation, circuits, and systems with collector-side base driven 有权
标题翻译：双向双基极双极结晶体管操作，电路和系统采用集电极侧驱动
公开(公告)号：US09190894B2
公开(公告)日：2015-11-17
申请号：US14735782
申请日：2015-06-10
申请人： Ideal Power Inc.
发明人： William C. Alexander , Richard A. Blanchard
IPC分类号： H01L29/86 , H02M1/088 , H01L29/73 , H03K17/66 , H03K3/012 , H02M3/158
CPC分类号： H02M3/158 , H01L27/0755 , H01L27/0823 , H01L27/0828 , H01L29/0619 , H01L29/0649 , H01L29/0804 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/16 , H01L29/1604 , H01L29/41708 , H01L29/42304 , H01L29/73 , H01L29/732 , H01L29/7375 , H01L29/7393 , H01L29/7395 , H02M1/088 , H02M3/1582 , H02M7/797 , H02M11/00 , H03K3/012 , H03K17/60 , H03K17/66 , H03K17/687
摘要： Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.
摘要翻译：用于使用双向双极晶体管（BTRAN）进行开关的功率分组开关电源转换器的方法，系统，电路和器件。四端子三层BTRAN在任一方向提供基本上相同的操作，正向电压小于二极管压降。 BTRAN是在非平衡载流子浓度高的条件下工作的完全对称的双对称双基极双极相对装置，当用作功率分组开关功率转换器的双向开关时，它可以具有惊人的协同作用。 BTRAN被驱动到高载流子浓度的状态，使得导通电压下降很低。

123. 发明授权

US09064923B2 Bipolar semiconductor component with a fully depletable channel zone 有权
标题翻译：具有完全消耗通道区的双极半导体元件
公开(公告)号：US09064923B2
公开(公告)日：2015-06-23
申请号：US13898862
申请日：2013-05-21
申请人： Infineon Technologies Austria AG
发明人： Roman Baburske , Josef Lutz , Ralf Siemieniec , Hans-Joachim Schulze
IPC分类号： H01L29/86 , H01L29/73 , H01L29/66 , H01L29/861
CPC分类号： H01L29/73 , H01L29/66136 , H01L29/861 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A bipolar semiconductor component includes a semiconductor body having first and second substantially parallel main surfaces and at least one load pn junction, a first metallization on the first surface, a second metallization on the second surface, and a current path running in the semiconductor body from the first metallization to the second metallization only through n-doped zones, including between first and second p-doped zones which are in contact with the first metallization and spaced apart from one another by an n-doped channel zone through which the current path runs. A space charge region forms in the semiconductor body between the first and second p-doped zones to fully deplete the n-doped channel zone between the first and second p-doped zones and therefore prevent current flow between the first and second metallizations along the current path when a positive voltage is applied between the second metallization and the first metallization.
摘要翻译：双极半导体部件包括半导体本体，该半导体本体具有第一和第二基本上平行的主表面和至少一个负载pn结，在第一表面上的第一金属化，第二表面上的第二金属化，以及在半导体本体中延伸的电流通路第一金属化到第二金属化仅通过n掺杂区，包括在与第一金属化接触并且通过电流路径运行的n掺杂沟道区彼此间隔开的第一和第二p掺杂区之间。空间电荷区域形成在第一和第二p掺杂区域之间的半导体本体中，以完全耗尽第一和第二p掺杂区域之间的n掺杂沟道区，并且因此防止沿着电流的第一和第二金属化之间的电流流动在第二金属化和第一金属化之间施加正电压时的路径。

124. 发明授权

US08816473B2 Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication 有权
标题翻译：用于精密电阻和电气保险丝的平面多晶硅区域及其制造方法
公开(公告)号：US08816473B2
公开(公告)日：2014-08-26
申请号：US13440172
申请日：2012-04-05
申请人： Arvind Kumar , Anthony I-Chih Chou , Renee T. Mo , Shreesh Narasimha
发明人： Arvind Kumar , Anthony I-Chih Chou , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： H01L23/5256 , H01L21/84 , H01L28/20 , H01L29/86 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections.
摘要翻译：公开了提供精密电阻元件的半导体结构和制造方法。多晶硅嵌入在硅衬底中。可以掺杂多晶硅以控制电阻。实施例可以包括电阻器，eFuse和绝缘体上硅结构。一些实施例可以包括非矩形横截面。

125. 发明申请

US20140110821A1 FOLDED CONICAL INDUCTOR 有权
公开(公告)号：US20140110821A1
公开(公告)日：2014-04-24
申请号：US13654529
申请日：2012-10-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Robert L. Barry , Robert A. Groves , Venkata N.R. Vanukuru
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： H01L29/86 , H01F17/0013 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor inductor structure may include a first spiral structure, located on a first metal layer, having a first outer-spiral electrically conductive track and a first inner-spiral electrically conductive track separated from the first outer-spiral electrically conductive track by a first dielectric material. A second spiral structure, located on a second metal layer, having a second outer-spiral electrically conductive track and a second inner-spiral electrically conductive track separated from the second outer-spiral electrically conductive track by a second dielectric material may also be provided. The first outer-spiral electrically conductive track may be electrically coupled to the second outer-spiral electrically conductive track and the first inner-spiral electrically conductive track may be electrically coupled to the second inner-spiral electrically conductive track. The first outer-spiral conductive track is laterally offset relative to the second outer-spiral conductive track and the first inner-spiral conductive track is laterally offset relative to the second inner-spiral conductive track.

126. 发明申请

US20140061853A1 PLATED LAMINATION STRUCTURES FOR INTEGRATED MAGNETIC DEVICES 有权
标题翻译：集成磁性装置的层压结构
公开(公告)号：US20140061853A1
公开(公告)日：2014-03-06
申请号：US13597412
申请日：2012-08-29
申请人： Bucknell C. Webb
发明人： Bucknell C. Webb
IPC分类号： H01F5/00 , H01L21/02 , H01L29/86
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01F2017/0066 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor integrated magnetic devices such as inductors, transformers, etc., having laminated magnetic-insulator stack structures are provided, wherein the laminated magnetic-insulator stack structures are formed using electroplating techniques. For example, an integrated laminated magnetic device includes a multilayer stack structure having alternating magnetic and insulating layers formed on a substrate, wherein each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by an insulating layer, and a local shorting structure to electrically connect each magnetic layer in the multilayer stack structure to an underlying magnetic layer in the multilayer stack structure to facilitate electroplating of the magnetic layers using an underlying conductive layer (magnetic or seed layer) in the stack as an electrical cathode/anode for each electroplated magnetic layer in the stack structure.
摘要翻译：提供具有层压的磁 - 绝缘体堆叠结构的诸如电感器，变压器等的半导体集成磁性器件，其中使用电镀技术形成层叠的磁性 - 绝缘体堆叠结构。例如，集成层叠磁性装置包括在基板上形成交替的磁性层和绝缘层的多层堆叠结构，其中多层堆叠结构中的每个磁性层通过绝缘层与多层堆叠结构中的另一磁性层分离，以及局部短路结构，以将多层堆叠结构中的每个磁性层电连接到多层堆叠结构中的下面的磁性层，以便利用叠层中的下面的导电层（磁性或种子层）作为电阴极来促进磁性层的电镀 /阳极，用于堆叠结构中的每个电镀磁性层。

127. 发明申请

US20140035097A1 SEMICONDUCTOR PACKAGE HAVING AN ANTENNA AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有天线的半导体封装及其制造方法
公开(公告)号：US20140035097A1
公开(公告)日：2014-02-06
申请号：US13564702
申请日：2012-08-01
申请人： I-Chia Lin , Sheng-Jian Jou , Han-Chee Yen
发明人： I-Chia Lin , Sheng-Jian Jou , Han-Chee Yen
IPC分类号： H01L29/86 , H01L21/78
CPC分类号： H01L23/552 , H01L21/568 , H01L23/295 , H01L23/3135 , H01L23/66 , H01L24/16 , H01L24/48 , H01L24/97 , H01L2223/6627 , H01L2223/6677 , H01L2224/16225 , H01L2224/48227 , H01L2224/97 , H01L2924/00014 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3011 , H01L2924/3025 , H01Q21/0087 , H01Q21/064 , H01Q21/065 , H01L2224/81 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment.
摘要翻译：提供半导体封装及其制造方法。半导体封装包括第一衬底，第二衬底，插入器衬底，半导体芯片，封装体和第一天线层。第一基板包括接地段。插入器基板设置在第二基板和第一基板之间。半导体芯片设置在第二基板上。封装体封装第二衬底，半导体芯片和插入器衬底，并且具有侧表面和上表面。第一天线层形成在封装主体的侧表面和上表面上，并且电连接到接地段。

128. 发明申请

US20130307117A1 Structure and Method for Inductors Integrated into Semiconductor Device Packages 审中-公开
标题翻译：集成到半导体器件封装中的电感器的结构和方法
公开(公告)号：US20130307117A1
公开(公告)日：2013-11-21
申请号：US13475439
申请日：2012-05-18
申请人： Sreenivasan KODURI
发明人： Sreenivasan KODURI
IPC分类号： H01L29/86 , H01L21/02 , H01L21/56 , H01F5/00
CPC分类号： H01L28/10 , H01F17/0006 , H01F17/04 , H01F2017/0086 , H01F2027/2814 , H01L23/3107 , H01L23/495 , H01L23/5227 , H01L23/645 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/45014 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/4813 , H01L2224/48247 , H01L2224/49113 , H01L2924/00014 , H01L2924/1461 , H01L2924/181 , H01L2924/19042 , H01L2924/19104 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/206
摘要： A thin-contour semiconductor device with a solenoid and iron core integrated into the device package. The solenoid windings are constructed by a stripe-shaped layer portion, deposited on the chip surface, and an arced wire portion welded to the layer portion by low-cost standard wire bonding technique. The stripes are arrayed parallel to each other, spaced apart respective insulating gaps. The arced wires span from one stripe to the adjacent next stripe by bridging the gap and keeping the clock direction constant. The arced solenoid windings are then integrated into the encapsulating device package. The ferromagnetic core may be shaped as a ring to allow the formation of a strong and nearly homogeneous magnetic field inside the solenoid, providing reliable energy storage for power supply circuits.
摘要翻译：具有集成到器件封装中的螺线管和铁芯的薄型半导体器件。螺线管绕组由沉积在芯片表面上的条状层部分和通过低成本标准引线接合技术焊接到层部分的弧形部分构成。条纹彼此平行排列，间隔开各自的绝缘间隙。通过桥接间隙并保持时钟方向恒定，弧形导线从一个条纹跨越到相邻的下一条纹。然后将弧形螺线管绕组集成到封装装置封装中。铁磁芯可以形成为环，以允许在螺线管内部形成强烈且几乎均匀的磁场，为电源电路提供可靠的能量存储。

129. 发明授权

US08575717B2 Integrated circuit device and method of manufacturing the same 有权
标题翻译：集成电路装置及其制造方法
公开(公告)号：US08575717B2
公开(公告)日：2013-11-05
申请号：US13090606
申请日：2011-04-20
申请人： Der-Chyang Yeh , Shang-Yun Hou
发明人： Der-Chyang Yeh , Shang-Yun Hou
IPC分类号： H01L29/86
CPC分类号： H01L23/5223 , H01L23/5227 , H01L27/08 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Provided is a integrated circuit device and a method for fabricating the same. The integrated circuit device includes a semiconductor substrate having a dielectric layer disposed over the semiconductor substrate and a passive element disposed over the dielectric layer. The integrated circuit further includes an isolation matrix structure, underlying the passive element, wherein the isolation matrix structure includes a plurality of trench regions each being formed through the dielectric layer and extending into the semiconductor substrate, the plurality of trench regions further including an insulating material and a void area.
摘要翻译：提供一种集成电路器件及其制造方法。集成电路器件包括具有设置在半导体衬底上的电介质层和设置在电介质层上的无源元件的半导体衬底。所述集成电路还包括在所述无源元件下面的隔离矩阵结构，其中所述隔离矩阵结构包括多个沟槽区，每个沟槽区通过所述电介质层形成并延伸到所述半导体衬底中，所述多个沟槽区还包括绝缘材料和空隙区域。

130. 发明申请

US20130264679A1 PLANAR POLYSILICON REGIONS FOR PRECISION RESISTORS AND ELECTRICAL FUSES AND METHOD OF FABRICATION 有权
标题翻译：用于精密电阻器和电熔体的平面多晶硅区域和制造方法
公开(公告)号：US20130264679A1
公开(公告)日：2013-10-10
申请号：US13440172
申请日：2012-04-05
申请人： Arvind Kumar , Anthony I. Chou , Renee T. Mo , Shreesh Narasimha
发明人： Arvind Kumar , Anthony I. Chou , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： H01L23/5256 , H01L21/84 , H01L28/20 , H01L29/86 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections.
摘要翻译：公开了提供精密电阻元件的半导体结构和制造方法。多晶硅嵌入在硅衬底中。可以掺杂多晶硅以控制电阻。实施例可以包括电阻器，eFuse和绝缘体上硅结构。一些实施例可以包括非矩形横截面。

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