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121. 发明申请

US20090091985A1 INPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND CONTROL METHOD OF THE SAME 有权
标题翻译：半导体存储器的输入电路及其控制方法
公开(公告)号：US20090091985A1
公开(公告)日：2009-04-09
申请号：US12107710
申请日：2008-04-22
申请人： Young Ju Kim
发明人： Young Ju Kim
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/14 , G11C29/48 , G11C29/56012 , G11C2029/5602
摘要： An input circuit of a semiconductor memory apparatus includes a first frequency control unit which receives a first signal and a second frequency control unit which receives a second signal. The first frequency control unit outputs the first signal to the second frequency control unit in response to a test mode signal and generates a third signal which has a frequency higher than the frequencies of the first and second signals by using the first and second signals. Also, the second frequency control unit outputs the second signal to the first frequency control unit in response to the test mode signal and generates a fourth signal which has a frequency higher than the frequencies of the first and second signals by using the first and second signals.
摘要翻译：半导体存储装置的输入电路包括接收第一信号的第一频率控制单元和接收第二信号的第二频率控制单元。第一频率控制单元响应于测试模式信号将第一信号输出到第二频率控制单元，并且通过使用第一和第二信号产生具有比第一和第二信号的频率高的频率的第三信号。此外，第二频率控制单元响应于测试模式信号将第二信号输出到第一频率控制单元，并且通过使用第一和第二信号产生具有高于第一和第二信号的频率的频率的第四信号。

122. 发明授权

US07509550B2 Fault diagnosis of compressed test responses 有权
标题翻译：压缩测试响应的故障诊断
公开(公告)号：US07509550B2
公开(公告)日：2009-03-24
申请号：US11213316
申请日：2005-08-25
申请人： Janusz Rajski , Grzegorz Mrugalski , Artur Pogiel , Jerzy Tyszer , Chen Wang
发明人： Janusz Rajski , Grzegorz Mrugalski , Artur Pogiel , Jerzy Tyszer , Chen Wang
IPC分类号： G01R31/3193 , G01R31/40
CPC分类号： G01R31/318547 , G01R31/31703 , G01R31/318536 , G01R31/318566 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.
摘要翻译：本文公开了用于诊断来自压缩测试响应的故障扫描单元的方法，装置和系统。例如，在一个非限制性示例性实施例中，接收到包括多个比特（包括一个或多个错误比特）的至少一个错误签名。使用搜索树来评估多个潜在错误位解释扫描单元候选。确定所评估的扫描单元候选中的一个或多个是否解释错误签名中的错误位，从而构成一个或多个故障扫描单元。由确定的任何这样的一个或多个故障扫描单元提供输出。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的有形计算机可读介质。还提供了包括由任何所公开的方法识别的故障扫描单元的列表的有形计算机可读介质。

123. 发明申请

US20090073796A1 MEMORY ARRAY PERIPHERAL STRUCTURES AND USE 失效
标题翻译：记忆阵列外围结构和使用
公开(公告)号：US20090073796A1
公开(公告)日：2009-03-19
申请号：US11856964
申请日：2007-09-18
申请人： Ishtiaq Ahsan , Louis Lu-Chen Hsu , Xu Ouyang
发明人： Ishtiaq Ahsan , Louis Lu-Chen Hsu , Xu Ouyang
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C5/02 , G11C5/06 , G11C29/006 , G11C29/24 , G11C29/48 , G11C29/808 , G11C29/816 , G11C29/838
摘要： A method for using photolithographic dummy memory cells arranged in rings around a set of primary memory cells as test structures and as redundant memory cells. Also circuits and structures of memory arrays having multiple-use dummy memory cells.
摘要翻译：一种使用设置在作为测试结构的一组主存储器单元周围的环的光刻虚拟存储单元的方法和作为冗余存储单元的方法。还有具有多次使用的虚拟存储器单元的存储器阵列的电路和结构。

124. 发明授权

US07499356B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07499356B2
公开(公告)日：2009-03-03
申请号：US11647685
申请日：2006-12-28
申请人： Chang-Ho Do
发明人： Chang-Ho Do
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/26 , G11C2029/1802
摘要： A semiconductor device includes a plurality of first pads; a plurality of ports for performing a serial data communication with external devices through the first pads; a plurality of banks for performing a parallel data communication with the plurality of ports; a plurality of global data buses for supporting the parallel data communication between the plurality of ports and the plurality of banks; and a test mode controller for performing a core test with various data transfer modes by converting the serial data communication into the parallel data communication during a core test mode.
摘要翻译：半导体器件包括多个第一焊盘; 用于通过第一焊盘执行与外部设备的串行数据通信的多个端口; 用于执行与所述多个端口的并行数据通信的多个存储体; 多个全球数据总线，用于支持多个端口和多个存储体之间的并行数据通信; 以及测试模式控制器，用于在核心测试模式期间通过将串行数据通信转换为并行数据通信来执行具有各种数据传输模式的核心测试。

125. 发明申请

US20090052263A1 Write driving circuit 有权
标题翻译：写驱动电路
公开(公告)号：US20090052263A1
公开(公告)日：2009-02-26
申请号：US12005700
申请日：2007-12-28
申请人： Taek Seung Kim
发明人： Taek Seung Kim
IPC分类号： G11C29/36
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/36
摘要： A write driving circuit is provided to drive a global input/output line to write same data to memory cells according to a combination of a first test data signal and a second test data signal in a test mode, regardless of input data signals.
摘要翻译：提供写入驱动电路以驱动全局输入/输出线，以在测试模式中根据第一测试数据信号和第二测试数据信号的组合将相同的数据写入存储器单元，而与输入数据信号无关。

126. 发明授权

US07466159B2 Semiconductor integrated circuit having multiple semiconductor chips with signal terminals 有权
标题翻译：具有多个具有信号端子的半导体芯片的半导体集成电路
公开(公告)号：US07466159B2
公开(公告)日：2008-12-16
申请号：US11586560
申请日：2006-10-26
申请人： Naoki Ito , Hideaki Ishihara , Yoshinori Teshima , Chikara Kobayashi
发明人： Naoki Ito , Hideaki Ishihara , Yoshinori Teshima , Chikara Kobayashi
IPC分类号： G01R31/02
CPC分类号： G11C5/066 , G01R31/31926 , G11C29/1201 , G11C29/48 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes: a package; semiconductor chips in the package including a signal terminal; and a wiring connecting signal terminals. One semiconductor chip is a test object chip including a probe terminal and a test object terminal. The probe terminal connects to an external terminal for testing the test object terminal. The test object chip further includes: a common wiring for connecting the probe terminal and the test object terminal; a first switch for connecting/disconnecting the probe terminal and the common wiring; a second switch for connecting/disconnecting the test object terminal and the common wiring; and a test signal interrupting element for interrupting the test signal to be inputted into an input circuit of the probe terminal.
摘要翻译：半导体集成电路包括：封装; 封装中的半导体芯片包括信号端子; 和连接信号端子的接线。一个半导体芯片是包括探针端子和测试对象端子的测试对象芯片。探头端子连接到外部端子，用于测试对象端子。测试对象芯片还包括：用于连接探针端子和测试对象端子的公共布线; 用于连接/断开探针端子和公共布线的第一开关; 用于连接/断开测试对象端子和公共布线的第二开关; 以及用于中断要输入到探头端子的输入电路的测试信号的测试信号中断元件。

127. 发明申请

US20080301509A1 METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUITS BY EMPLOYING TEST VECTOR PATTERNS THAT SATISFY PASSBAND REQUIREMENTS IMPOSED BY COMMUNICATION CHANNELS 有权
标题翻译：通过采用通信通道实现符合要求的测试矢量图来测试集成电路的方法和装置
公开(公告)号：US20080301509A1
公开(公告)日：2008-12-04
申请号：US11779629
申请日：2007-07-18
申请人： Bosco Chun Sang Lai , Sunny Lai-Ming Chang , Lawrence Wai Cheung Ho
发明人： Bosco Chun Sang Lai , Sunny Lai-Ming Chang , Lawrence Wai Cheung Ho
IPC分类号： G01R31/28
CPC分类号： G01R31/318342 , G11C29/12015 , G11C29/16 , G11C29/48 , G11C29/56 , G11C29/56012
摘要： Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication channel. A plurality of test vector patterns is generated having characteristics such that when a given test vector pattern is transmitted electrically at a transmission rate via the communication channel, the test vector pattern has a frequency content that is less than the frequency content of a high frequency test vector pattern if the high frequency test vector pattern were to be transmitted electrically at the transmission rate via the communication channel, and such that the frequency content of each test vector pattern when transmitted electrically at the transmission rate via the communication channel falls within the passband associated with the communication channel.
摘要翻译：本文描述了用于被测器件的高速测试的装置和方法的实施例，其中被测器件经受限通带通信信道耦合到测试器。产生多个测试向量模式，其特征在于，当经由通信信道以给定的测试向量模式以传输速率电传输时，测试矢量模式的频率内容小于高频测试的频率内容如果通过通信信道以传输速率电传送高频测试向量模式，并且使得当经由通信信道以传输速率电传输时，每个测试矢量模式的频率内容落入通带内与通信通道。

128. 发明申请

US20080288840A1 PROBELESS TESTING OF PAD BUFFERS ON WAFER 有权
标题翻译：垫片缓冲区的无阻试验
公开(公告)号：US20080288840A1
公开(公告)日：2008-11-20
申请号：US12182305
申请日：2008-07-30
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/303 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/31715 , G01R31/318505 , G01R31/318511 , G01R31/318533 , G01R31/318558 , G01R31/318572 , G01R31/318594 , G11C29/006 , G11C29/022 , G11C29/48 , G11C2029/3202
摘要： The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
摘要翻译：测试晶片上的集成电路管芯的外围电路（350,360，ESD，BH），而不会物理接触管芯的接合焊盘。

129. 发明授权

US07433252B2 Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device 失效
标题翻译：能够存储各种图案的数据的半导体存储器件以及对半导体存储器件进行电测试的方法
公开(公告)号：US07433252B2
公开(公告)日：2008-10-07
申请号：US11267203
申请日：2005-11-04
申请人： Gyu-Yeol Kim , Sang-Man Byun , Yong-Gyu Chu , Seok-Ho Park
发明人： Gyu-Yeol Kim , Sang-Man Byun , Yong-Gyu Chu , Seok-Ho Park
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/10 , G11C29/1201
摘要： A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.
摘要翻译：提供可以写入不同数据位的信息的半导体存储器件，以及电半导体存储器件的电测试方法。在用于测试半导体存储器件的存储单元阵列的模式中，半导体存储器包括一个控制信号生成焊盘，当数据被写入存储单元阵列时，该控制信号产生焊盘能够将不相同的数据写入每个组的数据输入/输出焊盘。

130. 发明授权

US07428181B2 Semiconductor device with self refresh test mode 失效
标题翻译：具有自刷新测试模式的半导体器件
公开(公告)号：US07428181B2
公开(公告)日：2008-09-23
申请号：US11181298
申请日：2005-07-14
申请人： Terry R. Lee
发明人： Terry R. Lee
IPC分类号： G11C11/406 , G11C29/08 , G11C29/12 , G11C8/18
CPC分类号： G11C29/028 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C29/02 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C2029/5002
摘要： A semiconductor device includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines.
摘要翻译：半导体器件包括具有动态存储单元的存储器阵列。在自刷新测试模式中，自刷新测试模式控制器监视和/或控制半导体器件中的各种块和内部信号。自刷新测试模式控制器可以通过包括一个或多个DQ线和/或一个或多个地址线的各种导体与远程测试设备进行通信。

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