专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

121. 发明申请

US20080189535A1 Method and System for Dependency Tracking and Flush Recovery for an Out-Of-Order Microprocessor 失效
标题翻译：用于无序微处理器的依赖跟踪和冲洗恢复的方法和系统
公开(公告)号：US20080189535A1
公开(公告)日：2008-08-07
申请号：US11669999
申请日：2007-02-01
申请人： Vikas Agarwal , William E. Burky , Krishnan Kailas , Balaram Sinharoy
发明人： Vikas Agarwal , William E. Burky , Krishnan Kailas , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3863
摘要： A method for dependency tracking and flush recovery for an out-of-order processor includes recording, in a last definition (DEF) data structure, an identifier of a first instruction as the most recent instruction in an instruction sequence that defines contents of the particular logical register and recording, in a next DEF data structure, the identifier of the first instruction in association with an identifier of a previous second instruction also indicating an update to the particular logical register. In addition, a recovery array is updated to indicate which of the instructions in the instruction sequence updates each of the plurality of logical registers. In response to misspeculation during execution of the instruction sequence, the processor performs a recovery operation to place the identifier of the second instruction in the last DEF data structure by reference to the next DEF data structure and the recovery array.
摘要翻译：用于无序处理器的依赖性跟踪和刷新恢复的方法包括在最后定义（DEF）数据结构中记录第一指令的标识符作为指定序列中的最新指令，其定义特定的内容在下一个DEF数据结构中，逻辑寄存器和记录与第一指令的标识符相关联，该标识符还指示特定逻辑寄存器的更新。此外，更新恢复阵列以指示指令序列中的哪些指令更新多个逻辑寄存器中的每一个。响应于执行指令序列期间的错误，处理器执行恢复操作，以通过参考下一个DEF数据结构和恢复阵列将第二指令的标识符放置在最后的DEF数据结构中。

122. 发明授权

US07401207B2 Apparatus and method for adjusting instruction thread priority in a multi-thread processor 有权
标题翻译：用于调整多线程处理器中指令线程优先级的装置和方法
公开(公告)号：US07401207B2
公开(公告)日：2008-07-15
申请号：US10424529
申请日：2003-04-25
申请人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
发明人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
IPC分类号： G06F9/40 , G06F9/44
CPC分类号： G06F9/4818 , G06F9/3851
摘要： Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between the threads according to some instruction interleave rule. However, upon the occurrence of some predefined event or circumstance in the processor related to a particular instruction thread, the base input processing priority of one or more instruction threads is adjusted to produce one more adjusted priority values. The instruction interleave rule is then enforced according to the adjusted priority value or values together with any base input processing priority values that have not been subject to adjustment.
摘要翻译： SMT处理器中的每个指令线程与软件分配的基本输入处理优先级相关联。除非正在处理或要处理的指令发生一些预定义的事件或情况，否则各个线程的基本输入处理优先级用于根据某种指令交错规则来确定线程之间的交织频率。然而，在与特定指令线程相关的处理器中发生某些预定义的事件或环境时，调整一个或多个指令线程的基本输入处理优先级以产生一个更多调整的优先级值。然后根据调整后的优先级值或与未经调整的任何基本输入处理优先级值一起实施指令交错规则。

123. 发明申请

US20080162904A1 APPARATUS FOR SELECTING AN INSTRUCTION THREAD FOR PROCESSING IN A MULTI-THREAD PROCESSOR 审中-公开
标题翻译：选择用于多线程处理器处理的指令螺纹的装置
公开(公告)号：US20080162904A1
公开(公告)日：2008-07-03
申请号：US12048171
申请日：2008-03-13
申请人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward
发明人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward
IPC分类号： G06F9/38
CPC分类号： G06F9/3851
摘要： The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave rule enforcement component produces at least one base instruction thread selection signal that indicates a particular one of the instruction threads for passing an instruction from that particular thread into a stream of interleaved instructions. Thread selection modification is provided by an interleave modification component that generates a final thread selection signal based upon the base thread selection signal and a feedback signal derived from one or more conditions or events in the various processor elements. This final thread selection signal may indicate the same instruction thread indicated by the base thread selection signal or a different one of the instruction threads for passing an instruction into the interleaved stream of instructions.
摘要翻译：可以修改SMT处理器中用于交织来自不同指令线程的指令的指令线程之间的选择以适应某些处理器事件或条件。在每个处理器时钟周期期间，交错规则实施部件产生至少一个基本指令线程选择信号，其指示用于将指令从该特定线程传递到交错指令流中的特定指令线程。线程选择修改由交织修改组件提供，交织修改组件基于基本线程选择信号和从各种处理器元件中的一个或多个条件或事件导出的反馈信号生成最后的线程选择信号。该最终线程选择信号可以指示由基线程选择信号指示的相同指令线程或用于将指令传递到交错指令流的指令线程中的不同指令线程。

124. 发明授权

US07392366B2 Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches 有权
标题翻译：多线程处理器中的自适应提取门控，提取控制和控制提取的方法
公开(公告)号：US07392366B2
公开(公告)日：2008-06-24
申请号：US11228781
申请日：2005-09-16
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard J. Eickemeyer , Lee E. Eisen , Philip G. Emma , John B. Griswell , Zhigang Hu , Hung Q. Le , Douglas R. Logan , Balaram Sinharoy
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard J. Eickemeyer , Lee E. Eisen , Philip G. Emma , John B. Griswell , Zhigang Hu , Hung Q. Le , Douglas R. Logan , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3867
摘要： A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches.
摘要翻译：多线程处理器，用于多线程处理器的获取控制以及在多线程处理器中获取的方法。监视处理器事件和使用（EU）符号，用于指示管道执行线程状态的下游管道条件。对于不能接收获取的高速缓存内容的任何线程，例如由于线程已满或停顿，跳过指令高速缓存提取。此外，可以针对相同的线程选择连续的提取，例如在分支误预测中。因此，处理器避免浪费电力不必要的或放置保持器提取。

125. 发明申请

US20080109640A1 Method For Changing A Thread Priority In A Simultaneous Multithread Processor 审中-公开
标题翻译：在同时多线程处理器中更改线程优先级的方法
公开(公告)号：US20080109640A1
公开(公告)日：2008-05-08
申请号：US12015088
申请日：2008-01-16
申请人： William Burky , Ronald Kalla , David Schroter , Balaram Sinharoy
发明人： William Burky , Ronald Kalla , David Schroter , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3865 , G06F9/30076 , G06F9/3009 , G06F9/3842 , G06F9/3851
摘要： An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in particular when the instruction has completed execution. To alter the priority of a thread, the software uses a special form of a “no operation” (NOP) instruction (hereafter termed thread priority NOP). When the thread priority NOP is dispatched, its special NOP is decoded in the decode unit of the IDU into an operation that writes a special code into the completion table for the thread priority NOP. A “trouble” bit is also set in the completion table that indicates which instruction group contains the thread priority NOP. The trouble bit indicates that special processing is required after instruction completion. The thread priority instruction is processed after completion using the special code to change a thread's priority.
摘要翻译： SMT系统旨在允许软件更改线程优先级。在一种情况下，系统基于指令执行的状态，特别是当指令完成执行时，发出线程优先级的改变。要更改线程的优先级，软件使用特殊形式的“无操作”（NOP）指令（以下称为线程优先级NOP）。当调度线程优先级NOP时，其特殊NOP在IDU的解码单元中解码为将特殊代码写入线程优先级NOP的完成表的操作。在完成表中也设置了“故障”位，指示哪个指令组包含线程优先级NOP。故障位表示指令完成后需要进行特殊处理。线程优先级指令在完成后使用特殊代码进行处理，以更改线程的优先级。

126. 发明授权

US07287122B2 Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing 失效
标题翻译：多处理器NUCA系统中的数据复制，以减少水平缓存的颠簸
公开(公告)号：US07287122B2
公开(公告)日：2007-10-23
申请号：US10960611
申请日：2004-10-07
申请人： Ramakrishnan Rajamony , Xiaowei Shen , Balaram Sinharoy
发明人： Ramakrishnan Rajamony , Xiaowei Shen , Balaram Sinharoy
IPC分类号： G06F15/163 , G06F13/36
CPC分类号： G06F12/0846 , G06F12/0813 , G06F12/084 , G06F12/122 , G06F2212/271
摘要： A method of managing a distributed cache structure having separate cache banks, by detecting that a given cache line has been repeatedly accessed by two or more processors which share the cache, and replicating that cache line in at least two separate cache banks. The cache line is optimally replicated in a cache bank having the lowest latency with respect to the given accessing processor. A currently accessed line in a different cache bank can be exchanged with a cache line in the cache bank with the lowest latency, and another line in the cache bank with lowest latency is moved to the different cache bank prior to the currently accessed line being moved to the cache bank with the lowest latency. Further replication of the cache line can be disabled when two or more processors alternately write to the cache line.
摘要翻译：一种通过检测给定的高速缓存行已被共享高速缓存的两个或多个处理器重复访问并且在至少两个单独的高速缓冲存储器中复制该高速缓存行的方式来管理具有单独的高速缓存组的分布式高速缓存结构的方法。高速缓存行被优化地复制到相对于给定访问处理器具有最低延迟的缓存组中。在不同的缓存组中的当前访问的行可以与具有最低延迟的高速缓存组中的高速缓存行交换，并且具有最低延迟的高速缓存组中的另一行在当前访问的行被移动之前移动到不同的高速缓存组以最低的延迟到达缓存库。当两个或更多个处理器交替写入高速缓存行时，可以禁用高速缓存行的进一步复制。

127. 发明申请

US20070150659A1 Cache injection semi-synchronous memory copy operation 失效
标题翻译：缓存注入半同步内存复制操作
公开(公告)号：US20070150659A1
公开(公告)日：2007-06-28
申请号：US11316070
申请日：2005-12-22
申请人： Ravi Arimilli , Rama Govindaraju , Peter Hochschild , Bruce Mealey , Satya Sharma , Balaram Sinharoy
发明人： Ravi Arimilli , Rama Govindaraju , Peter Hochschild , Bruce Mealey , Satya Sharma , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F9/30032 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F12/0862 , G06F12/0888 , G06F12/0897 , G06F2212/6028
摘要： A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous memory copy operation is checked for a given value in at least one cache injection bit. In response to the given value in the cache injection bit, a predefined number of lines of destination data is copied into at least one level of cache memory.
摘要翻译：公开了一种基于半同步存储器复制指令中的信息将数据插入高速缓冲存储器的系统，方法和计算机。该方法包括确定半同步存储器复制操作的开始。在至少一个高速缓存注入位中检查给定值的半同步存储器复制操作。响应于高速缓存注入位中的给定值，预定数量的目的地数据行被复制到至少一级的高速缓存存储器中。

128. 发明授权

US07228388B2 Enabling and disabling cache bypass using predicted cache line usage 失效
标题翻译：使用预测的缓存线路使用启用和禁用缓存旁路
公开(公告)号：US07228388B2
公开(公告)日：2007-06-05
申请号：US10993531
申请日：2004-11-19
申请人： Zhigang Hu , John T. Robinson , Xiaowei Shen , Balaram Sinharoy
发明人： Zhigang Hu , John T. Robinson , Xiaowei Shen , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0897
摘要： Arrangements and method for enabling and disabling cache bypass in a computer system with a cache hierarchy. Cache bypass status is identified with respect to at least one cache line. A cache line identified as cache bypass enabled is transferred to one or more higher level caches of the cache hierarchy, whereby a next higher level cache in the cache hierarchy is bypassed, while a cache line identified as cache bypass disabled is transferred to one or more higher level caches of the cache hierarchy, whereby a next higher level cache in the cache hierarchy is not bypassed. Included is an arrangement for selectively enabling or disabling cache bypass with respect to at least one cache line based on historical cache access information.
摘要翻译：在具有缓存层次结构的计算机系统中启用和禁用缓存旁路的安排和方法。相对于至少一个高速缓存行来标识缓存旁路状态。标识为启用高速缓存旁路的高速缓存线路被传送到高速缓存层级的一个或多个较高级别的高速缓存，由此旁路高速缓存层级中的下一个较高级别的高速缓存，而被识别为高速缓存旁路禁用的高速缓存线路被转移到一个或多个高速缓存层级的更高级别的高速缓存，从而不绕过高速缓存层级中的下一级高速缓存。包括一种用于基于历史缓存访问信息选择性地启用或禁用相对于至少一个高速缓存行的高速缓存旁路的装置。

129. 发明授权

US07194587B2 Localized cache block flush instruction 有权
标题翻译：本地化缓存块刷新指令
公开(公告)号：US07194587B2
公开(公告)日：2007-03-20
申请号：US10422677
申请日：2003-04-24
申请人： John David McCalpin , Balaram Sinharoy , Dereck Edward Williams , Kenneth Lee Wright
发明人： John David McCalpin , Balaram Sinharoy , Dereck Edward Williams , Kenneth Lee Wright
IPC分类号： G06F12/00
CPC分类号： G06F9/30047 , G06F12/0804 , G06F12/0808 , G06F12/0837 , G06F12/0891
摘要： A microprocessor and a related compiler support a local cache block flush instruction in which an execution unit of a processor determines an effective address. The processor forces all pending references to a cache block corresponding to the determined effective address to commit to the cache subsystem. If the referenced cache line is modified in the local cache (the cache subsystem corresponding to the processor executing the instruction), it is then written back to main memory. If the referenced block is valid in the local cache it is invalidated, but only in the local cache. If the referenced block is not valid in the local cache, there is no invalidation. Remote processors receiving a local cache block flush instruction from another processor via the system ignore the instruction.
摘要翻译：微处理器和相关编译器支持本地缓存块刷新指令，其中处理器的执行单元确定有效地址。处理器强制所有未决引用对应于所确定的有效地址的缓存块以提交到缓存子系统。如果引用的高速缓存行在本地缓存（与执行指令的处理器相对应的缓存子系统）中被修改，则将其写回主存储器。如果引用的块在本地缓存中有效，则它将被无效，但仅在本地缓存中。如果引用的块在本地缓存中无效，则不会产生无效。通过系统从另一个处理器接收本地缓存块刷新指令的远程处理器忽略该指令。

130. 发明授权

US07120784B2 Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment 失效
标题翻译：通过在同时多线程处理环境中逻辑分割分支历史表和预测目标地址缓存来进行线程专用分支预测
公开(公告)号：US07120784B2
公开(公告)日：2006-10-10
申请号：US10425064
申请日：2003-04-28
申请人： Gregory William Alexander , Scott Bruce Frommer , David Stephen Levitan , Balaram Sinharoy
发明人： Gregory William Alexander , Scott Bruce Frommer , David Stephen Levitan , Balaram Sinharoy
IPC分类号： G06F9/40 , G06F9/00
CPC分类号： G06F9/3806 , G06F9/30189 , G06F9/3844 , G06F9/3851
摘要： Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better results for branch prediction. The branch prediction logic responds to the occurrence of the monitored condition by logically splitting the BHTs and count cache so that half of the address space is allocated to a first thread and the second half is allocated to the next thread. Prediction-generated addresses that belong to the first thread are then directed to the half of the array that is allocated to that thread and prediction-generated addresses that belong to the second thread are directed to the next half of the array that is allocated to the second thread. In order to split the array, the highest order bit in the array is utilized to uniquely identify addresses of the first and the second threads.
摘要翻译：分支预测逻辑被增强以提供用于某些条件的监视功能，其指示使用单独的BHT和预测的目标地址高速缓存将为分支预测提供更好的结果。分支预测逻辑通过逻辑分割BHT和计数高速缓存来响应监视条件的发生，使得一半的地址空间被分配给第一个线程，而后半部分被分配给下一个线程。属于第一个线程的预测生成的地址然后被定向到分配给该线程的数组的一半，并且属于第二个线程的预测生成的地址被定向到分配给该线程的数组的下一半第二线程。为了拆分阵列，阵列中的最高位用于唯一标识第一和第二个线程的地址。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式