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121. 发明申请

US20080285330A1 METHODS OF OPERATING A BISTABLE RESISTANCE RANDOM ACCESS MEMORY WITH MULTIPLE MEMORY LAYERS AND MULTILEVEL MEMORY STATES 有权
标题翻译：具有多个存储层和多个存储器状态的双向电阻随机存取存储器的操作方法
公开(公告)号：US20080285330A1
公开(公告)日：2008-11-20
申请号：US12134117
申请日：2008-06-05
申请人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsien
发明人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsien
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C17/165 , B82Y10/00 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/0069 , G11C17/16 , G11C2213/31 , G11C2213/32 , G11C2213/77
摘要： A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f) R. The logic “1” state is represented by a mathematical expression (n+f) R. The logic “2” state is represented by a mathematical expression (1+nf) R. The logic “3” state is represented by a mathematical expression n(1+f) R.
摘要翻译：描述了一种用于操作具有串联排列的两个存储层堆叠的双稳态电阻随机存取存储器的方法。双稳态电阻随机存取存储器包括每个存储单元的两个存储层堆栈，双稳态电阻随机存取存储器以四个逻辑状态，逻辑“00”状态，逻辑“01”状态，逻辑“10”状态和逻辑 “11”状态。逻辑“0”状态由数学表达式（1 + f）R表示。逻辑“1”状态为由数学表达式（n + f）R表示。逻辑“2”状态由数学表达式（1 + nf）R表示。逻辑“3”状态由数学表达式n（1 + f）R 。

122. 发明申请

US20080173931A1 Multilevel-Cell Memory Structures Employing Multi-Memory Layers with Tungsten Oxides and Manufacturing Method 有权
标题翻译：使用氧化钨的多存储器层的多层单元存储器结构和制造方法
公开(公告)号：US20080173931A1
公开(公告)日：2008-07-24
申请号：US11625216
申请日：2007-01-19
申请人： ChiaHua Ho , Erh-Kun Lai
发明人： ChiaHua Ho , Erh-Kun Lai
IPC分类号： H01L27/00 , H01L21/44
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2481 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/1633
摘要： The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.
摘要翻译：本发明提供具有多个存储层结构的多电平单元存储器结构，其中每个存储层结构包括为多个逻辑状态定义不同读取电流电平的氧化钨区域。每个存储器层结构可以通过使用提供多电平单元功能的氧化钨区域来提供构成四个逻辑状态的两位信息，其中四个逻辑状态等于四个不同的读取电流电平。具有两个存储器层结构的存储器结构将提供四位存储位置和16个逻辑状态。在一个实施例中，第一和第二存储层结构中的每一个包括延伸到钨插塞构件的主表面中的钨氧化物区域，其中钨插塞的外表面被阻挡构件包围。

123. 发明申请

US20080002477A1 METHOD FOR MANUFACTURING MEMORY CELL 有权
标题翻译：制造记忆细胞的方法
公开(公告)号：US20080002477A1
公开(公告)日：2008-01-03
申请号：US11836142
申请日：2007-08-09
申请人： Tzu-Hsuan Hsu , Erh-Kun Lai , Hang-Ting Lue , Chia-Hua Ho
发明人： Tzu-Hsuan Hsu , Erh-Kun Lai , Hang-Ting Lue , Chia-Hua Ho
IPC分类号： G11C11/34 , H01L21/36
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/42352
摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.
摘要翻译：本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构底物。存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。跨门位于基板上，跨越垂直翅片结构。载体捕获层位于跨门和基板之间。源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

124. 发明申请

US20070262388A1 Bridge Resistance Random Access Memory Device and Method With A Singular Contact Structure 有权
标题翻译：桥接电阻随机存取存储器件及其具有奇异接触结构的方法
公开(公告)号：US20070262388A1
公开(公告)日：2007-11-15
申请号：US11382422
申请日：2006-05-09
申请人： ChiaHua Ho , Erh-Kun Lai , Kuang Hsieh
发明人： ChiaHua Ho , Erh-Kun Lai , Kuang Hsieh
IPC分类号： H01L23/62 , H01L21/338
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second electrode is located within an interior of the circumferential extending shape and separated from the first electrode by an insulating material. A resistance memory bridge is in contact with an edge surface of the first and second electrodes. The first electrode in the contact structure is connected to a transistor and the second electrode in the contact structure is connected to a bit line. A bit line is connected to the second electrode by a self-aligning process.
摘要翻译：公开了一种桥结构中的电阻随机存取存储器，其包括其中第一和第二电极位于接触结构内的接触结构。第一电极具有围绕接触结构的内壁的周向延伸形状，例如环形形状。第二电极位于周向延伸形状的内部，并通过绝缘材料与第一电极分离。电阻记忆桥与第一和第二电极的边缘表面接触。接触结构中的第一电极连接到晶体管，并且接触结构中的第二电极连接到位线。位线通过自对准工艺连接到第二电极。

125. 发明申请

US20060205157A1 Non-volatile memory and method for fabricating the same 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20060205157A1
公开(公告)日：2006-09-14
申请号：US11429070
申请日：2006-05-05
申请人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
发明人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42348 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.
摘要翻译：提供非易失性存储器。存储器包括衬底，电介质层，导电层，隔离层，掩埋位线，隧道电介质层，电荷俘获层，势垒介电层和字线。其中介电层设置在基板上。导电层设置在电介质层上。隔离层设置在基板上并且邻近电介质层和导电层。掩埋位线设置在衬底中并在隔离层下方。隧道电介质层设置在导电层和隔离层的基板和侧壁上。电荷捕获层设置在隧道介电层上，势垒介电层设置在电荷俘获层上。字线设置在基板上，与埋入位线交叉。

126. 发明申请

US20060197180A1 THREE-DIMENSIONAL MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：三维存储器结构及其制造方法
公开(公告)号：US20060197180A1
公开(公告)日：2006-09-07
申请号：US11307221
申请日：2006-01-27
申请人： Erh-Kun Lai , Ming-Chung Liang
发明人： Erh-Kun Lai , Ming-Chung Liang
IPC分类号： H01L29/00
CPC分类号： H01L27/1021 , H01L21/8221 , H01L23/5252 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional memory structure and manufacturing method thereof is provided. A first stack layer is formed over a substrate. The first stack layer includes, from the substrate upwards, an n-type polysilicon layer, a conductive layer, an anti-fuse and another n-type polysilicon layer. The first stack layer is patterned to form a first stack circuit. Thereafter, a second stack layer is formed over the first stack circuit. The second stack layer includes, from the first stack circuit upwards, a p-type polysilicon layer, a conductive layer, an anti-fuse and another p-type polysilicon. The second stack layer is patterned to form a second stack circuit that crosses over the first stack circuit perpendicularly. The aforementioned steps are repeated to form more stack circuits above the substrate and hence produce a three-dimensional structure.
摘要翻译：提供三维记忆结构及其制造方法。第一堆叠层形成在衬底上。第一堆叠层从衬底向上包括n型多晶硅层，导电层，反熔丝和另一n型多晶硅层。图案化第一堆叠层以形成第一堆叠电路。此后，在第一堆叠电路上形成第二堆叠层。第二堆叠层从第一堆叠电路向上包括p型多晶硅层，导电层，反熔丝和另一p型多晶硅。图案化第二堆叠层以形成垂直于第一堆叠电路的第二堆叠电路。重复上述步骤以在衬底上形成更多的堆叠电路，并因此产生三维结构。

127. 发明授权

US07067375B1 Non-volatile memory and method for fabricating the same 有权
公开(公告)号：US07067375B1
公开(公告)日：2006-06-27
申请号：US11018507
申请日：2004-12-20
申请人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
发明人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42348 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

128. 发明授权

US06566225B2 Formation method of shallow trench isolation 有权
标题翻译：浅沟隔离的形成方法
公开(公告)号：US06566225B2
公开(公告)日：2003-05-20
申请号：US09921580
申请日：2001-08-06
申请人： Erh-Kun Lai , Hsin-Huei Chen , Yu-Ping Huang
发明人： Erh-Kun Lai , Hsin-Huei Chen , Yu-Ping Huang
IPC分类号： H01L21336
CPC分类号： H01L21/76224
摘要： The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide layer is formed thereon. A second polysilicon layer is formed on the oxide layer. The partial second polysilicon layer, the oxide layer, the first polysilicon layer, and the pad oxide layer are removed to expose the partial substrate. The second polysilicon layer and the partial substrate are etched for forming the trench structure in the substrate. An etched depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.
摘要翻译：本发明提供一种沟槽结构的形成方法，包括在衬底上形成衬垫氧化物层。在衬垫氧化物层上形成第一多晶硅层，在其上形成氧化物层。在氧化物层上形成第二多晶硅层。去除部分第二多晶硅层，氧化物层，第一多晶硅层和衬垫氧化物层以暴露部分衬底。蚀刻第二多晶硅层和部分衬底以在衬底中形成沟槽结构。沟槽结构的蚀刻深度由第二多晶硅层的蚀刻厚度很好地控制。

129. 发明授权

US08816423B2 Semiconducting multi-layer structure and method for manufacturing the same 有权
标题翻译：半导体多层结构及其制造方法
公开(公告)号：US08816423B2
公开(公告)日：2014-08-26
申请号：US13584366
申请日：2012-08-13
申请人： Erh-Kun Lai , Yen-Hao Shih
发明人： Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and a lateral surface. The first insulating layers surround the peripherals of the first conductive layers. Each of the first insulating layers covers at least a part of the upper surface of each of the first conductive layers, at least a part of the bottom surface of each of the first conductive layers and the two lateral surface of each of the first conductive layers. The second conductive layer covers the first conductive layers and the first insulating layers.
摘要翻译：公开了一种包括多个第一导电层，多个第一绝缘层和第二导电层的半导体多层结构。第一导电层分开设置。每个第一导电层具有上表面，与上表面相对的底表面和侧表面。第一绝缘层围绕第一导电层的外围设备。每个第一绝缘层覆盖每个第一导电层的上表面的至少一部分，每个第一导电层的底表面的至少一部分和每个第一导电层的两个侧表面。第二导电层覆盖第一导电层和第一绝缘层。

130. 发明授权

US08597976B2 Multilevel-cell memory structures employing multi-memory layers with tungsten oxides and manufacturing method 有权
标题翻译：采用钨氧化物多层记忆层的多层单元记忆结构及制造方法
公开(公告)号：US08597976B2
公开(公告)日：2013-12-03
申请号：US12683007
申请日：2010-01-06
申请人： ChiaHua Ho , Erh-Kun Lai
发明人： ChiaHua Ho , Erh-Kun Lai
IPC分类号： H01L21/00 , H01L21/16
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2481 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/1633
摘要： The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.
摘要翻译：本发明提供具有多个存储层结构的多电平单元存储器结构，其中每个存储层结构包括为多个逻辑状态定义不同读取电流电平的氧化钨区域。每个存储器层结构可以通过使用提供多电平单元功能的氧化钨区域来提供构成四个逻辑状态的两位信息，其中四个逻辑状态等于四个不同的读取电流电平。具有两个存储器层结构的存储器结构将提供四位存储位置和16个逻辑状态。在一个实施例中，第一和第二存储层结构中的每一个包括延伸到钨插塞构件的主表面中的钨氧化物区域，其中钨插塞的外表面被阻挡构件包围。

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