专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080285330A1 METHODS OF OPERATING A BISTABLE RESISTANCE RANDOM ACCESS MEMORY WITH MULTIPLE MEMORY LAYERS AND MULTILEVEL MEMORY STATES 有权
标题翻译：具有多个存储层和多个存储器状态的双向电阻随机存取存储器的操作方法
公开(公告)号：US20080285330A1
公开(公告)日：2008-11-20
申请号：US12134117
申请日：2008-06-05
申请人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsien
发明人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsien
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C17/165 , B82Y10/00 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/0069 , G11C17/16 , G11C2213/31 , G11C2213/32 , G11C2213/77
摘要： A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f) R. The logic “1” state is represented by a mathematical expression (n+f) R. The logic “2” state is represented by a mathematical expression (1+nf) R. The logic “3” state is represented by a mathematical expression n(1+f) R.
摘要翻译：描述了一种用于操作具有串联排列的两个存储层堆叠的双稳态电阻随机存取存储器的方法。双稳态电阻随机存取存储器包括每个存储单元的两个存储层堆栈，双稳态电阻随机存取存储器以四个逻辑状态，逻辑“00”状态，逻辑“01”状态，逻辑“10”状态和逻辑 “11”状态。逻辑“0”状态由数学表达式（1 + f）R表示。逻辑“1”状态为由数学表达式（n + f）R表示。逻辑“2”状态由数学表达式（1 + nf）R表示。逻辑“3”状态由数学表达式n（1 + f）R 。

2. 发明授权

US08243494B2 Self-aligned structure and method for confining a melting point in a resistor random access memory 有权
标题翻译：用于将熔点限制在电阻随机存取存储器中的自对准结构和方法
公开(公告)号：US08243494B2
公开(公告)日：2012-08-14
申请号：US12235773
申请日：2008-09-23
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
IPC分类号： G11C16/02 , H01L29/417
CPC分类号： H01L45/06 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.
摘要翻译：制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料，选择性材料。柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

3. 发明授权

US08178405B2 Resistor random access memory cell device 有权
标题翻译：电阻随机存取存储单元器件
公开(公告)号：US08178405B2
公开(公告)日：2012-05-15
申请号：US12755897
申请日：2010-04-07
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： H01L21/8242
CPC分类号： H01L45/122 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/144 , H01L45/1625 , H01L45/1641 , H01L45/1683
摘要： A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film.
摘要翻译：存储单元装置具有底部电极和顶部电极，与底部电极接触的存储器材料的插头以及具有接触顶部电极的边缘和接触存储器的底部开口的杯形导电构件材料。因此，存储单元中的导电路径从顶部电极通过导电杯状构件，并通过相变材料的塞子到达底部电极。此外，用于制造存储单元器件的方法包括在底部电极上形成包括绝缘元件和止动元件的底部电极岛的步骤，形成围绕岛的分离层，去除止动元件以在绝缘元件上方形成孔在分离层中，在孔中形成导电膜，在导电膜上形成绝缘衬垫，进行蚀刻以形成具有边缘的杯形导电膜，并且通过绝缘衬垫和杯状导电体的底部形成开口在底部电极的表面形成薄膜，在开口中形成相变记忆材料塞，形成与杯状导电膜的边缘接触的顶部电极。

4. 发明授权

US08139393B2 Method and apparatus for non-volatile multi-bit memory 有权
标题翻译：用于非易失性多位存储器的方法和装置
公开(公告)号：US08139393B2
公开(公告)日：2012-03-20
申请号：US12576212
申请日：2009-10-08
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C2213/31 , G11C2213/32 , G11C2213/34 , G11C2213/79 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/122 , H01L45/144 , H01L45/146 , H01L45/1633
摘要： A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer.
摘要翻译：可选择地显示第一和第二逻辑电平的存储器件。第一导电材料具有形成在其上的第一存储层的第一表面，并且第二导电材料具有形成在其上的第二存储层的第二表面。连接导电层连接第一和第二存储层并将其放置在电接触中。该结构被设计成使得第一存储层的横截面积小于第二存储层的横截面面积。

5. 发明授权

US07972893B2 Memory device manufacturing method 有权
标题翻译：存储器件制造方法
公开(公告)号：US07972893B2
公开(公告)日：2011-07-05
申请号：US12469184
申请日：2009-05-20
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang-Yeu Hsieh
IPC分类号： H01L21/00
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A method for making a memory device includes providing a dielectric material, having first and second upwardly and inwardly tapering surfaces and a surface segment connecting the first and second surfaces. First and second electrodes are formed over the first and second surfaces. A memory element is formed over the surface segment to electrically connect the first and second electrodes.
摘要翻译：制造存储器件的方法包括提供具有第一和第二向上和向内渐缩的表面的电介质材料以及连接第一和第二表面的表面段。第一和第二电极形成在第一和第二表面上。存储元件形成在表面段上以电连接第一和第二电极。

6. 发明授权

US07923285B2 Method for forming self-aligned thermal isolation cell for a variable resistance memory array 有权
标题翻译：用于形成用于可变电阻存储器阵列的自对准热隔离单元的方法
公开(公告)号：US07923285B2
公开(公告)日：2011-04-12
申请号：US12351692
申请日：2009-01-09
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1683
摘要： A non-volatile memory with a self-aligned RRAM element includes a lower electrode element, generally planar in form, having an inner contact surface; an upper electrode element, spaced from the lower electrode element; a containment structure extends between the upper electrode element and the lower electrode element, with a sidewall spacer element having a generally funnel-shaped central cavity with a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode. A RRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element.
摘要翻译：具有自对准RRAM元件的非易失性存储器包括具有内接触表面的大体平面形状的下电极元件; 与所述下电极元件间隔开的上电极元件; 容纳结构在上电极元件和下电极元件之间延伸，侧壁间隔元件具有大致漏斗形的具有中心孔的中心腔; 以及位于侧壁间隔元件和下电极之间的突出元件。 RRAM元件在下电极元件和上电极之间延伸，占据侧壁间隔件元件中心腔的至少一部分并且从侧壁间隔件端子边缘朝向和与下电极接触。以这种方式，伞形元件内表面与RRAM元件间隔开以限定与RRAM元件相邻的热隔离单元。

7. 发明申请

US20090101883A1 Method for manufacturing a resistor random access memory with a self-aligned air gap insulator 有权
标题翻译：具有自对准气隙绝缘体的电阻随机存取存储器的制造方法
公开(公告)号：US20090101883A1
公开(公告)日：2009-04-23
申请号：US11977088
申请日：2007-10-23
申请人： Erh Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： H01L21/28 , H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/148
摘要： A memory device including a programmable resistive memory material is described along with methods for manufacturing the memory device. A memory device disclosed herein includes top and bottom electrodes and a multilayer stack disposed between the top and bottom electrodes. The multilayer stack includes a memory element comprising programmable resistive memory material and has a sidewall surface. An air gap is adjacent to the sidewall surface and self-aligned to the memory element.
摘要翻译：包括可编程电阻性存储器材料的存储器件与用于制造存储器件的方法一起被描述。本文公开的存储器件包括顶部和底部电极以及设置在顶部和底部电极之间的多层叠层。多层堆叠包括存储元件，其包括可编程电阻存储器材料并具有侧壁表面。气隙与侧壁表面相邻并且与存储元件自对准。

8. 发明申请

US20070257300A1 Structures and Methods of a Bistable Resistive Random Access Memory 有权
标题翻译：双稳态电阻随机存取存储器的结构和方法
公开(公告)号：US20070257300A1
公开(公告)日：2007-11-08
申请号：US11381973
申请日：2006-05-05
申请人： ChiaHua Ho , Erh-Kun Lai , Kuang Hsieh
发明人： ChiaHua Ho , Erh-Kun Lai , Kuang Hsieh
IPC分类号： H01L29/788 , H01L21/336 , H01L21/8234 , H01L21/8244
CPC分类号： H01L27/101 , H01L27/24 , H01L45/04 , H01L45/145
摘要： Structures and methods to form a bistable resistive random access memory for reducing the amount of heat dissipation from electrodes by confining a heating region in the memory cell device are described. The heating region is confined in a kernel comprising a programmable resistive memory material that is in contact with an upper programmable resistive memory member and a lower programmable resistive memory member. The lower programmable resistive member has sides that align with sides of a bottom electrode comprising a tungsten plug. The lower programmable resistive member and the bottom electrode function a first conductor so that the amount of heat dissipation from the first conductor is reduced. The upper programmable resistive memory material and a top electrode function as a second conductor so that the amount of heat dissipation from the second conductor is reduced.
摘要翻译：描述了形成双稳态电阻随机存取存储器的结构和方法，用于通过将加热区限制在存储单元装置中来减少从电极散热的量。加热区域被限制在包括与上可编程电阻存储器构件和下可编程电阻存储器构件接触的可编程电阻性存储器材料的内核中。下部可编程电阻构件具有与包括钨插件的底部电极的侧面对准的侧面。下可编程电阻构件和底电极起第一导体的作用，使得来自第一导体的散热量减小。上部可编程电阻性存储器材料和顶部电极用作第二导体，使得来自第二导体的散热量减少。

9. 发明授权

US08597976B2 Multilevel-cell memory structures employing multi-memory layers with tungsten oxides and manufacturing method 有权
标题翻译：采用钨氧化物多层记忆层的多层单元记忆结构及制造方法
公开(公告)号：US08597976B2
公开(公告)日：2013-12-03
申请号：US12683007
申请日：2010-01-06
申请人： ChiaHua Ho , Erh-Kun Lai
发明人： ChiaHua Ho , Erh-Kun Lai
IPC分类号： H01L21/00 , H01L21/16
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2481 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/1633
摘要： The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.
摘要翻译：本发明提供具有多个存储层结构的多电平单元存储器结构，其中每个存储层结构包括为多个逻辑状态定义不同读取电流电平的氧化钨区域。每个存储器层结构可以通过使用提供多电平单元功能的氧化钨区域来提供构成四个逻辑状态的两位信息，其中四个逻辑状态等于四个不同的读取电流电平。具有两个存储器层结构的存储器结构将提供四位存储位置和16个逻辑状态。在一个实施例中，第一和第二存储层结构中的每一个包括延伸到钨插塞构件的主表面中的钨氧化物区域，其中钨插塞的外表面被阻挡构件包围。

10. 发明授权

US08461564B2 Memory devices having an embedded resistance memory with metal-oxygen compound 有权
标题翻译：具有金属氧化合物的嵌入电阻记忆体的存储器件
公开(公告)号：US08461564B2
公开(公告)日：2013-06-11
申请号：US12855630
申请日：2010-08-12
申请人： ChiaHua Ho , Erh-Kun Lai
发明人： ChiaHua Ho , Erh-Kun Lai
IPC分类号： H01L47/00
CPC分类号： H01L45/1683 , B82Y10/00 , G11C11/14 , G11C11/22 , G11C11/5685 , G11C13/0007 , G11C2213/32 , G11C2213/51 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.
摘要翻译：描述了基于氧化钨存储区域的存储器件以及用于制造的方法以及用于编程这种器件的方法。在一些实施例中，氧化钨存储区可以通过使用非关键掩模氧化钨材料或甚至根本不进行掩模来形成。本文描述的存储器件包括底部电极和底部电极上的存储元件。存储元件包括至少一种钨 - 氧化合物，并且可编程为至少两个电阻状态。包含阻挡材料的顶部电极在存储元件上，阻挡材料防止金属离子从顶部电极移动到存储元件中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式